Mahmut Yilmaz

30 papers A 8B 1C 1Misc 7Journal 5Unranked 5
YearRankTypeTitle / Venue / Authors
2024 A conf
A Scalable & Cost Efficient Next-Gen Scan Architecture: Streaming Scan Test via NVIDIA MATHS.
ITC
Kunal Jain Mangilal, Mahmut Yilmaz, Vishal Agarwal, Shantanu Sarangi, Kaushik Narayanun
2023 J jnl
NVIDIA MATHS: Mechanism to Access Test-Data Over High-Speed Links.
IEEE Des. Test
Mahmut Yilmaz, Pavan Kumar Datla Jagannadha, Kaushik Narayanun, Shantanu Sarangi, Francisco Da Silva, Joe Sarmiento
2022 Misc conf
NVIDIA MATHS: Mechanism to Access Test-Data over High-Speed Links.
VTS
Mahmut Yilmaz, Pavan Kumar Datla Jagannadha, Kaushik Narayanun, Shantanu Sarangi, Francisco Da Silva, Joe Sarmiento, Smbat Tonoyan, Ashwin Chintaluri, Animesh Khare, Milind Sonawane, Ashish Kumar, Anitha Kalva, Alex Hsu, Jayesh Pandey
2022 Misc conf
On-Die Noise Measurement During Automatic Test Equipment (ATE) Testing and In-System-Test (IST).
VTS
Seyed Nima Mozaffari, Bonita Bhaskaran, Shantanu Sarangi, Suhas M. Satheesh, Kuo Lin Fu, Nithin Valentine, P. Manikandan, Mahmut Yilmaz
2019 Misc conf
Special Session: In-System-Test (IST) Architecture for NVIDIA Drive-AGX Platforms.
VTS
Pavan Kumar Datla Jagannadha, Mahmut Yilmaz, Milind Sonawane, Sailendra Chadalavada, Shantanu Sarangi, Bonita Bhaskaran, Shashank Bajpai, Venkat Abilash Reddy Nerallapally, Jayesh Pandey, Sam Jiang
2016 A conf
Advanced test methodology for complex SoCs.
ITC
Pavan Kumar Datla Jagannadha, Mahmut Yilmaz, Milind Sonawane, Sailendra Chadalavada, Shantanu Sarangi, Bonita Bhaskaran, Ayub Abdollahian
2016 Misc conf
Dynamic docking architecture for concurrent testing and peak power reduction.
VTS
Milind Sonawane, Pavan Kumar Datla Jagannadha, Sailendra Chadalavada, Shantanu Sarangi, Mahmut Yilmaz, Amit Sanghani, Karthikeyan Natarajan, Jonathon E. Colburn, Anubhav Sinha
2016 Misc conf
Flexible scan interface architecture for complex SoCs.
VTS
Milind Sonawane, Sailendra Chadalavada, Shantanu Sarangi, Amit Sanghani, Mahmut Yilmaz, Pavan Kumar Datla Jagannadha, Jonathon E. Colburn
2014 — ch.
Circuit Path Grading Considering Layout, Process Variations, and Cross Talk.
Testing for Small-Delay Defects in Nanoscale CMOS Integrated Circuits
Ke Peng, Mahmut Yilmaz, Mohammad Tehranipoor
2014 — ch.
Output Deviations-Based SDD Testing.
Testing for Small-Delay Defects in Nanoscale CMOS Integrated Circuits
Mahmut Yilmaz
2013 J jnl
Crosstalk- and Process Variations-Aware High-Quality Tests for Small-Delay Defects.
IEEE Trans. Very Large Scale Integr. Syst.
Ke Peng, Mahmut Yilmaz, Krishnendu Chakrabarty, Mohammad Tehranipoor
2013 J jnl
Efficient Pattern Generation for Small-Delay Defects Using Selection of Critical Faults.
J. Electron. Test.
Fang Bao, Ke Peng, Mahmut Yilmaz, Krishnendu Chakrabarty, LeRoy Winemberg, Mohammad Tehranipoor
2012 — conf
Robust Timing-Aware Test Generation Using Pseudo-Boolean Optimization.
Asian Test Symposium
Stephan Eggersglüß, Mahmut Yilmaz, Krishnendu Chakrabarty
2011 J jnl
A Metric to Target Small-Delay Defects in Industrial Circuits.
IEEE Des. Test Comput.
Mahmut Yilmaz, Mohammad Tehranipoor, Krishnendu Chakrabarty
2011 B conf
Critical Fault-Based Pattern Generation for Screening SDDs.
ETS
Fang Bao, Ke Peng, Mahmut Yilmaz, Krishnendu Chakrabarty, LeRoy Winemberg, Mohammad Tehranipoor
2010 — conf
A Noise-Aware Hybrid Method for SDD Pattern Grading and Selection.
Asian Test Symposium
Ke Peng, Mahmut Yilmaz, Krishnendu Chakrabarty, Mohammad Tehranipoor
2010 Misc conf
A novel hybrid method for SDD pattern grading and selection.
VTS
Ke Peng, Jason Thibodeau, Mahmut Yilmaz, Krishnendu Chakrabarty, Mohammad Tehranipoor
2010 — conf
Circuit Topology-Based Test Pattern Generation for Small-Delay Defects.
Asian Test Symposium
Sandeep Kumar Goel, Krishnendu Chakrabarty, Mahmut Yilmaz, Ke Peng, Mohammad Tehranipoor
2010 A conf
High-quality pattern selection for screening small-delay defects considering process variations and crosstalk.
DATE
Ke Peng, Mahmut Yilmaz, Mohammad Tehranipoor, Krishnendu Chakrabarty
2010 A conf
RT-level design-for-testability and expansion of functional test sequences for enhanced defect coverage.
ITC
Alodeep Sanyal, Krishnendu Chakrabarty, Mahmut Yilmaz, Hideo Fujiwara
2010 J jnl
Test-Pattern Selection for Screening Small-Delay Defects in Very-Deep Submicrometer Integrated Circuits.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Mahmut Yilmaz, Krishnendu Chakrabarty, Mohammad Tehranipoor
2010 A conf
The scan-DFT features of AMD's next-generation microprocessor core.
ITC
Mahmut Yilmaz, Baosheng Wang, Jayalakshmi Rajaraman, Tom Olsen, Kanwaldeep Sobti, Dwight Elvey, Jeff Fitzgerald, Grady Giles, Wei-Yu Chen
2009 — —
Automated Test Grading and Pattern Selection for Small-Delay Defects.
Mahmut Yilmaz
2009 A conf
Seed selection in LFSR-reseeding-based test compression for the detection of small-delay defects.
DATE
Mahmut Yilmaz, Krishnendu Chakrabarty
2008 A conf
Interconnect-Aware and Layout-Oriented Test-Pattern Selection for Small-Delay Defects.
ITC
Mahmut Yilmaz, Krishnendu Chakrabarty, Mohammad Tehranipoor
2008 Misc conf
Test-Pattern Grading and Pattern Selection for Small-Delay Defects.
VTS
Mahmut Yilmaz, Krishnendu Chakrabarty, Mohammad Tehranipoor
2007 — conf
Lazy Error Detection for Microprocessor Functional Units.
DFT
Mahmut Yilmaz, Albert Meixner, Sule Ozev, Daniel J. Sorin
2007 C conf
Low-cost run-time diagnosis of hard delay faults in the functional units of a microprocessor.
ICCD
Sule Ozev, Daniel J. Sorin, Mahmut Yilmaz
2006 — conf
Applying architectural vulnerability Analysis to hard faults in the microprocessor.
SIGMETRICS/Performance
Fred A. Bower, Derek Hower, Mahmut Yilmaz, Daniel J. Sorin, Sule Ozev
2006 A conf
Self-Checking and Self-Diagnosing 32-bit Microprocessor Multiplier.
ITC
Mahmut Yilmaz, Derek Hower, Sule Ozev, Daniel J. Sorin