Mahmut E. Sinangil

28 papers A* 1B 2Journal 13Unranked 11

Year	Rank	Type	Title / Venue / Authors
2025	—	`conf`	17.6 A 100MHz Self-Calibrating RC Oscillator Capable of Clock-Glitch Detection for Hardware Security in a 3nm FinFET Process. ISSCC Nandish Mehta, Stephen G. Tell, Sanquan Song, Sudhir S. Kudva, Brian Zimmer, Mahmut E. Sinangil, C. Thomas Gray
2021	J	`jnl`	A 7-nm Compute-in-Memory SRAM Macro Supporting Multi-Bit Input, Weight and Output and Achieving 351 TOPS/W and 372.4 GOPS. IEEE J. Solid State Circuits Mahmut E. Sinangil, Burak Erbagci, Rawan Naous, Kerem Akarvardar, Dar Sun, Win-San Khwa, Hung-Jen Liao, Yih Wang, Jonathan Chang
2021	—	`conf`	An 89TOPS/W and 16.3TOPS/mm ISSCC Yu-Der Chih, Po-Hao Lee, Hidehiro Fujiwara, Yi-Chun Shih, Chia-Fu Lee, Rawan Naous, Yu-Lin Chen, Chieh-Pu Lo, Cheng-Han Lu, Haruki Mori, Wei-Cheng Zhao, Dar Sun, Mahmut E. Sinangil, Yen-Huei Chen, Tan-Li Chou, Kerem Akarvardar, Hung-Jen Liao, Yih Wang, Meng-Fan Chang, Tsung-Yung Jonathan Chang
2020	—	`conf`	15.3 A 351TOPS/W and 372.4GOPS Compute-in-Memory SRAM Macro in 7nm FinFET CMOS for Machine-Learning Applications. ISSCC Qing Dong, Mahmut E. Sinangil, Burak Erbagci, Dar Sun, Win-San Khwa, Hung-Jen Liao, Yih Wang, Jonathan Chang
2019	J	`jnl`	A 1-Mb 28-nm 1T1MTJ STT-MRAM With Single-Cap Offset-Cancelled Sense Amplifier and In Situ Self-Write-Termination. IEEE J. Solid State Circuits Qing Dong, Zhehong Wang, Jongyup Lim, Yiqun Zhang, Mahmut E. Sinangil, Yi-Chun Shih, Yu-Der Chih, Tsung-Yung Jonathan Chang, David T. Blaauw, Dennis Sylvester
2019	J	`jnl`	A 290-mV, 7-nm Ultra-Low-Voltage One-Port SRAM Compiler Design Using a 12T Write Contention and Read Upset Free Bit-Cell. IEEE J. Solid State Circuits Mahmut E. Sinangil, Yen-Ting Lin, Hung-Jen Liao, Jonathan Chang
2018	—	`conf`	A 290MV Ultra-Low Voltage One-Port SRAM Compiler Design Using a 12T Write Contention and Read Upset Free Bit-Cell in 7NM FinFET Technology. VLSI Circuits Mahmut E. Sinangil, Yen-Ting Lin, Hung-Jen Liao, Jonathan Chang
2017	J	`jnl`	Energy-Efficient Reconfigurable SRAM: Reducing Read Power Through Data Statistics. IEEE J. Solid State Circuits Chuhong Duan, Andreas J. Gotterba, Mahmut E. Sinangil, Anantha P. Chandrakasan
2016	J	`jnl`	A 28 nm 2 Mbit 6 T SRAM With Highly Configurable Low-Voltage Write-Ability Assist Implementation and Capacitor-Based Sense-Amplifier Input Offset Compensation. IEEE J. Solid State Circuits Mahmut E. Sinangil, John W. Poulton, Matthew R. Fojtik, Thomas H. Greer, Stephen G. Tell, Andreas J. Gotterba, Jesse Wang, Jason Golbus, Brian Zimmer, William J. Dally, C. Thomas Gray
2016	—	`conf`	Reconfigurable, conditional pre-charge SRAM: Lowering read power by leveraging data statistics. A-SSCC Chuhong Duan, Andreas J. Gotterba, Mahmut E. Sinangil, Anantha P. Chandrakasan
2014	—	`conf`	A reverse write assist circuit for SRAM dynamic write VMIN tracking using canary SRAMs. ISQED Arijit Banerjee, Mahmut E. Sinangil, John W. Poulton, C. Thomas Gray, Benton H. Calhoun
2014	—	`conf`	A self-aware processor SoC using energy monitors integrated into power converters for self-adaptation. VLSIC Yildiz Sinangil, Sabrina M. Neuman, Mahmut E. Sinangil, Nathan Ickes, George Bezerra, Eric Lau, Jason E. Miller, Henry Hoffmann, Srinivas Devadas, Anantha P. Chandrakasan
2014	J	`jnl`	Application-Specific SRAM Design Using Output Prediction to Reduce Bit-Line Switching Activity and Statistically Gated Sense Amplifiers for Up to 1.9× Lower Energy/Access. IEEE J. Solid State Circuits Mahmut E. Sinangil, Anantha P. Chandrakasan
2013	—	`conf`	An SRAM using output prediction to reduce BL-switching activity and statistically-gated SA for up to 1.9× reduction in energy/access. ISSCC Mahmut E. Sinangil, Anantha P. Chandrakasan
2013	J	`jnl`	Cost and Coding Efficient Motion Estimation Design Considerations for High Efficiency Video Coding (HEVC) Standard. IEEE J. Sel. Top. Signal Process. Mahmut E. Sinangil, Vivienne Sze, Minhua Zhou, Anantha P. Chandrakasan
2012	J	`jnl`	A 28 nm 0.6 V Low Power DSP for Mobile Applications. IEEE J. Solid State Circuits Nathan Ickes, Gordon Gammie, Mahmut E. Sinangil, Rahul Rithe, Jie Gu, Alice Wang, Hugh Mair, Satyendra Datla, Bing Rong, Sushma Honnavara Prasad, Lam Ho, Greg Baldwin, Dennis Buss, Anantha P. Chandrakasan, Uming Ko
2012	J	`jnl`	Design of Low-Voltage Digital Building Blocks and ADCs for Energy-Efficient Systems. IEEE Trans. Circuits Syst. II Express Briefs Mahmut E. Sinangil, Marcus Yip, Masood Qazi, Rahul Rithe, Joyce Kwong, Anantha P. Chandrakasan
2012	B	`conf`	Hardware-aware motion estimation search algorithm development for high-efficiency video coding (HEVC) standard. ICIP Mahmut E. Sinangil, Anantha P. Chandrakasan, Vivienne Sze, Minhua Zhou
2012	—	`—`	Low-power and application-specific SRAM design for energy-efficient motion estimation. Mahmut E. Sinangil
2012	B	`conf`	Memory cost vs. coding efficiency trade-offs for HEVC motion estimation engine. ICIP Mahmut E. Sinangil, Anantha P. Chandrakasan, Vivienne Sze, Minhua Zhou
2012	A*	`conf`	Self-aware computing in the Angstrom processor. DAC Henry Hoffmann, Jim Holt, George Kurian, Eric Lau, Martina Maggio, Jason E. Miller, Sabrina M. Neuman, Mahmut E. Sinangil, Yildiz Sinangil, Anant Agarwal, Anantha P. Chandrakasan, Srinivas Devadas
2011	—	`conf`	A 28nm 0.6V low-power DSP for mobile applications. ISSCC Gordon Gammie, Nathan Ickes, Mahmut E. Sinangil, Rahul Rithe, Jie Gu, Alice Wang, Hugh Mair, Satyendra Datla, Bing Rong, Sushma Honnavara Prasad, Lam Ho, Greg Baldwin, Dennis Buss, Anantha P. Chandrakasan, Uming Ko
2011	—	`conf`	A 28nm high-density 6T SRAM with optimized peripheral-assist circuits for operation down to 0.6V. ISSCC Mahmut E. Sinangil, Hugh Mair, Anantha P. Chandrakasan
2011	J	`jnl`	Challenges and Directions for Low-Voltage SRAM. IEEE Des. Test Comput. Masood Qazi, Mahmut E. Sinangil, Anantha P. Chandrakasan
2010	J	`jnl`	Technologies for Ultradynamic Voltage Scaling. Proc. IEEE Anantha P. Chandrakasan, Denis C. Daly, Daniel F. Finchelstein, Joyce Kwong, Yogesh K. Ramadass, Mahmut E. Sinangil, Vivienne Sze, Naveen Verma
2009	J	`jnl`	A 0.7-V 1.8-mW H.264/AVC 720p Video Decoder. IEEE J. Solid State Circuits Vivienne Sze, Daniel F. Finchelstein, Mahmut E. Sinangil, Anantha P. Chandrakasan
2009	J	`jnl`	A Reconfigurable 8T Ultra-Dynamic Voltage Scalable (U-DVS) SRAM in 65 nm CMOS. IEEE J. Solid State Circuits Mahmut E. Sinangil, Naveen Verma, Anantha P. Chandrakasan
2008	—	`conf`	A reconfigurable 65nm SRAM achieving voltage scalability from 0.25-1.2V and performance scalability from 20kHz-200MHz. ESSCIRC Mahmut E. Sinangil, Naveen Verma, Anantha P. Chandrakasan