Mahesh Mehendale

62 papers A* 5A 6B 2C 3Misc 23Journal 8Unranked 15

Year	Rank	Type	Title / Venue / Authors
2025	J	`jnl`	HOMI: Ultra-Fast EdgeAI platform for Event Cameras. CoRR Shankaranarayanan H, Satyapreet Singh Yadav, Adithya Krishna, Ajay Vikram P, Mahesh Mehendale, Chetan Singh Thakur
2025	J	`jnl`	Neural Signal Compression using RAMAN tinyML Accelerator for BCI Applications. CoRR Adithya Krishna, Sohan Debnath, André van Schaik, Mahesh Mehendale, Chetan Singh Thakur
2024	C	`conf`	Live Demonstration: Real-time audio and visual inference on the RAMAN TinyML accelerator. ISCAS Adithya Krishna, Ashwin Rajesh, Hitesh Pavan Oleti, Anand Chauhan, Shankaranarayanan H, André van Schaik, Mahesh Mehendale, Chetan Singh Thakur
2024	J	`jnl`	RAMAN: A Reconfigurable and Sparse tinyML Accelerator for Inference on Edge. IEEE Internet Things J. Adithya Krishna, Srikanth Rohit Nudurupati, Chandana D. G, Pritesh Dwivedi, André van Schaik, Mahesh Mehendale, Chetan Singh Thakur
2023	—	`conf`	A Sparsity-driven tinyML Accelerator for Decoding Hand Kinematics in Brain-Computer Interfaces. BioCAS Adithya Krishna, Vignesh Ramanathan, Satyapreet Singh Yadav, Sahil Shah, André van Schaik, Mahesh Mehendale, Chetan Singh Thakur
2023	—	`conf`	Live Demonstration: Audio Inference using Neuromorphic Cochlea on RAMAN Accelerator. BioCAS Adithya Krishna, Hitesh Pavan Oleti, Anand Chauhan, H. Shankaranarayanan, André van Schaik, Mahesh Mehendale, Chetan Singh Thakur
2023	J	`jnl`	RAMAN: A Re-configurable and Sparse tinyML Accelerator for Inference on Edge. CoRR Adithya Krishna, Srikanth Rohit Nudurupati, Chandana D. G, Pritesh Dwivedi, André van Schaik, Mahesh Mehendale, Chetan Singh Thakur
2022	—	`conf`	An area-efficient 6T-SRAM based Compute-In-Memory architecture with reconfigurable SAR ADCs for energy-efficient deep neural networks in edge ML applications. CICC Avishek Biswas, Hetul Sanghvi, Mahesh Mehendale, G. Preet
2021	Misc	`conf`	150nA IQ, Quad Input - Quad Output, Intelligent Integrated Power Management for IoT Applications. VLSID Vipul Singhal, Rajat Chauhan, Vinod Menezes, R. R. Manikandan, Raveesh Magod, Mahesh Mehendale, Anantha P. Chandrakasan
2020	—	`conf`	DBQ: A Differentiable Branch Quantizer for Lightweight Deep Neural Networks. ECCV (27) Hassan Dbouk, Hetul Sanghvi, Mahesh Mehendale, Naresh R. Shanbhag
2020	J	`jnl`	DBQ: A Differentiable Branch Quantizer for Lightweight Deep Neural Networks. CoRR Hassan Dbouk, Hetul Sanghvi, Mahesh Mehendale, Naresh R. Shanbhag
2018	Misc	`conf`	A 1.2 pJ/cycle KHz Timer Circuit for Heavily Duty-Cycled Systems. VLSID R. R. Manikandan, Vipul Kumar Singhal, Rajat Chauhan, Vinod Menezes, Mahesh Mehendale
2017	—	`conf`	Session 14 overview: Deep-learning processors. ISSCC Takashi Hashimoto, Mahesh Mehendale, Byeong-Gyu Nam
2016	—	`conf`	F1: Designing secure systems: Manufacturing, circuits and architectures. ISSCC Vivek De, Kerry Bernstein, Takefumi Yoshikawa, Yusuf Leblebici, Marian Verhelst, Mahesh Mehendale, Makoto Nagata
2016	—	`conf`	MicroRefresh: Minimizing Refresh Overhead in DRAM Caches. MEMSYS Nagendra Gulur, R. Govindarajan, Mahesh Mehendale
2016	—	`conf`	Session 4 overview: Digital processors. ISSCC Mahesh Mehendale, Luke Shin
2015	—	`conf`	8.3 A 10.5μA/MHz at 16MHz single-cycle non-volatile memory access microcontroller with full state retention at 108nA in a 90nm process. ISSCC Vipul Kumar Singhal, Vinod Menezes, Srinivasa Chakravarthy, Mahesh Mehendale
2015	B	`conf`	A Comprehensive Analytical Performance Model of DRAM Caches. ICPE Nagendra Dwarakanath Gulur, Mahesh Mehendale, Ramaswamy Govindarajan
2015	C	`conf`	Accelerating H.264/HEVC video slice processing using application specific instruction set processor. ICCE Dipan Kumar Mandal, Mihir Mody, Mahesh Mehendale, Naresh Yadav, Ghone Chaitanya, Piyali Goswami, Hetul Sanghvi, Niraj Nandan
2014	C	`conf`	A 28nm programmable and low power ultra-HD video codec engine. ISCAS Hetul Sanghvi, Mihir N. Mody, Niraj Nandan, Mahesh Mehendale, Subrangshu Das, Dipan Kumar Mandal, Pavan Shastry
2014	Misc	`conf`	A monolithic programmable Ultra-HD video codec engine. ICASSP Hetul Sanghvi, Mihir N. Mody, Niraj Nandan, Mahesh Mehendale, Subrangshu Das, Dipan Kumar Mandal, Nainala Vyagrheswarudu, Vijayavardhan Baireddy, Pavan Shastry
2014	A*	`conf`	ANATOMY: an analytical model of memory system performance. SIGMETRICS Nagendra Gulur, Mahesh Mehendale, Raman Manikantan, Ramaswamy Govindarajan
2014	A*	`conf`	Bi-Modal DRAM Cache: Improving Hit Rate, Hit Latency and Bandwidth. MICRO Nagendra Dwarakanath Gulur, Mahesh Mehendale, R. Manikantan, R. Govindarajan
2012	—	`conf`	A true multistandard, programmable, low-power, full HD video-codec engine for smartphone SoC. ISSCC Mahesh Mehendale, Subrangshu Das, Mohit Sharma, Mihir N. Mody, Ratna Reddy, Joseph P. Meehan, Hideo Tamama, Brian Carlson, Mike Polley
2012	A	`conf`	Multiple sub-row buffers in DRAM: unlocking performance and energy improvement opportunities. ICS Nagendra Dwarakanath Gulur, R. Manikantan, Mahesh Mehendale, R. Govindarajan
2011	J	`jnl`	Memory Bandwidth and Power Reduction Using Lossy Reference Frame Compression in Video Encoding. IEEE Trans. Circuits Syst. Video Technol. Ajit Gupte, Bharadwaj Amrutur, Mahesh Mehendale, Ajit V. Rao, Madhukar Budagavi
2011	B	`conf`	Row-Buffer Reorganization: Simultaneously Improving Performance and Reducing Energy in DRAMs. PACT Nagendra Dwarakanath Gulur, R. Manikantan, R. Govindarajan, Mahesh Mehendale
2006	J	`jnl`	Area and Power Reduction of Embedded DSP Systems using Instruction Compression and Re-configurable Encoding. J. VLSI Signal Process. Subash Chandar G., Mahesh Mehendale, R. Govindarajan
2006	Misc	`conf`	SoC - The Road Ahead. VLSI Design Mahesh Mehendale
2004	Misc	`conf`	Challenges in the Design of Embedded Real-time DSP SoCs. VLSI Design Mahesh Mehendale
2003	A*	`conf`	Emerging markets: design goes global. DAC Chi-Foon Chan, Deirdre Hanford, Jian Yue Pan, Narendra V. Shenoy, Mahesh Mehendale, A. Vasudevan, Shaojun Wei
2003	A	`conf`	Multivoltage scheduling with voltage-partitioned variable storage. ISLPED Amitabh Menon, S. K. Nandy, Mahesh Mehendale
2001	A	`conf`	Area and Power Reduction of Embedded DSP Systems using Instruction Compression and Re-Configurable Encoding. ICCAD Subash Chandar G., Mahesh Mehendale, R. Govindarajan
2001	Misc	`conf`	Functional Verification of Programmable DSP Cores. VLSI Design Mahesh Mehendale, Santhosh Kumar Amanna
2001	Misc	`conf`	High Level Synthesis Of Multi-Precision Data Flow Graphs. VLSI Design Vikas Agrawal, Anand Pande, Mahesh Mehendale
2001	Misc	`conf`	Performance Considerations in Embedded DSP based System-On-a-Chip Designs. VLSI Design Ajit Gupte, Mahesh Mehendale, Ramesh Ramamritham, Deepa Nair
2000	Misc	`conf`	Low Power Realization of Residue Number System Based FIR Filters. VLSI Design M. N. Mahesh, Mahesh Mehendale
2000	Misc	`conf`	Power Reduction Techniques for Portable DSP Applications. VLSI Design Mahesh Mehendale, Sunil D. Sherlekar
1999	Misc	`conf`	Improving Area Efficiency of Residue Number System based Implementation of DSP Algorithms. VLSI Design M. N. Mahesh, Satrajit Gupta, Mahesh Mehendale
1999	—	`conf`	Improving performance of high precision signal processing algorithms on programmable DSPs. ISCAS (3) M. N. Mahesh, Mahesh Mehendale
1999	—	`conf`	Integrated IC design approach based on software engineering paradigm. CICC Sunsil Sinha, Mahesh Mehendale
1999	Misc	`conf`	Low Power Code Generation of Multiplication-free Linear Transforms. VLSI Design Mahesh Mehendale, Sunil D. Sherlekar
1998	Misc	`conf`	Algorithmic and Architectural Transformations for Low Power Realization of FIR Filters. VLSI Design Mahesh Mehendale, Sunil D. Sherlekar, G. Venkatesh
1998	Misc	`conf`	Coefficient Transformations for Area-Efficient Implementation of Multiplier-less FIR Filters. VLSI Design Mahesh Mehendale, Somdipta Basu Roy, Sunil D. Sherlekar, G. Venkatesh
1998	Misc	`conf`	Extensions to Programmable DSP architectures for Reduced Power Dissipation. VLSI Design Mahesh Mehendale, Sunil D. Sherlekar, G. Venkatesh
1998	—	`conf`	Low Power Realization of FIR Filters Implemented using Distributed Arithmetic. ASP-DAC Mahesh Mehendale, Amit Sinha, Sunil D. Sherlekar
1998	J	`jnl`	Low-power realization of FIR filters on programmable DSPs. IEEE Trans. Very Large Scale Integr. Syst. Mahesh Mehendale, Sunil D. Sherlekar, G. Venkatesh
1998	Misc	`conf`	mproving Area Efficiency of FIR Filters Implemented Using Distributed Arithmetic. VLSI Design Amit Sinha, Mahesh Mehendale
1997	Misc	`conf`	Area-Delay Tradeoff in Distributed Arithmetic Based Implementation of FIR Filters. VLSI Design Mahesh Mehendale, Sunil D. Sherlekar, G. Venkatesh
1996	Misc	`conf`	Low power realization of FIR filters using multirate architectures. VLSI Design Mahesh Mehendale, Sunil D. Sherlekar, G. Venkatesh
1996	A*	`conf`	Optimized Code Generation of Multiplication-free Linear Transforms. DAC Mahesh Mehendale, G. Venkatesh, Sunil D. Sherlekar
1995	Misc	`conf`	AATMA: an algorithm for technology mapping for antifuse-based FPGAs. VLSI Design Mahesh Mehendale, M. K. Ram Prasad
1995	A	`conf`	Synthesis of multiplier-less FIR filters with minimum number of additions. ICCAD Mahesh Mehendale, Sunil D. Sherlekar, G. Venkatesh
1995	—	`conf`	Techniques for low power realization for FIR filters. ASP-DAC Mahesh Mehendale, Sunil D. Sherlekar, G. Venkatesh
1994	Misc	`conf`	An Integrated Approach to State Assignment and Sequential Element Selection for FSM Synthesis. VLSI Design Mahesh Mehendale, Biswadip Mitra
1994	Misc	`conf`	Impact of Logic Module Routing Flexibility on the Routability of Antifuse-Based Channelled FPGA Architectures. VLSI Design Mahesh Mehendale
1993	Misc	`conf`	Estimating Area Efficiency of Antifuse Based Channelled FPGA Architectures. VLSI Design Mahesh Mehendale, Kaushik Roy
1993	A*	`conf`	MIM: Logic Module Independent Technology Mapping for Design and Evaluation of Antifuse-based FPGAs. DAC Mahesh Mehendale
1992	Misc	`conf`	A System for Behavior Extraction from FPGA Implementations of Synchronous Designs. VLSI Design Mahesh Mehendale
1991	—	`conf`	An approach to design flow management in CAD frameworks. EURO-DAC Mahesh Mehendale
1991	A	`conf`	SLIM: A System for ASIC Library Management. ICCAD Mahesh Mehendale, P. Murugavel, M. Poornima
1989	A	`conf`	FDT-a design tool for switched capacitor filters. ICCAD Sattam Dasgupta, Mahesh Mehendale, V. R. Sudershan, Rajeev Jain, Nagaraj Subramanyam, James Hochschild