Mahesh A. Iyer

37 papers A* 2A 7B 5C 1Misc 3Journal 6Unranked 13

Year	Rank	Type	Title / Venue / Authors
2025	Misc	`conf`	A Partitioning-Based CAD Flow for Interposer-Based Multi-Die FPGAs. FCCM Mahesh A. Iyer, Andrew B. Kahng, Jason Luu, Bodhisatta Pramanik, Kristofer Vorwerk, Grace Zgheib
2025	B	`conf`	ARC: A Runtime Engine for Accelerating Independent Multi-Agent Reinforcement Learning on Multi-Core Processors. ICPADS Samuel Wiggins, Nikunj Gupta, Grace Zgheib, Mahesh A. Iyer, Viktor K. Prasanna
2025	—	`conf`	Accelerating Independent Multi-Agent Reinforcement Learning on Multi-GPU Platforms. Euro-Par (3) Samuel Wiggins, Nikunj Gupta, Grace Zgheib, Mahesh A. Iyer, Viktor K. Prasanna
2025	J	`jnl`	An Acceleration Framework for Deep Reinforcement Learning Using Heterogeneous Systems. IEEE Trans. Parallel Distributed Syst. Yuan Meng, Mahesh A. Iyer, Viktor K. Prasanna
2025	B	`conf`	Double Duty: FPGA Architecture to Enable Concurrent LUT and Adder Chain Usage. FPL Junius Pun, Xilai Dai, Grace Zgheib, Mahesh A. Iyer, Andrew Boutros, Vaughn Betz, Mohamed S. Abdelfattah
2025	J	`jnl`	Double Duty: FPGA Architecture to Enable Concurrent LUT and Adder Chain Usage. CoRR Junius Pun, Xilai Dai, Grace Zgheib, Mahesh A. Iyer, Andrew Boutros, Vaughn Betz, Mohamed S. Abdelfattah
2024	B	`conf`	A Heterogeneous Acceleration System for Attention-Based Multi-Agent Reinforcement Learning. FPL Samuel Wiggins, Yuan Meng, Mahesh A. Iyer, Viktor K. Prasanna
2024	B	`conf`	Better Together: Combining Analytical and Annealing Methods for FPGA Placement. FPL Rachel Selina Rajarathnam, Kate Thurmer, Vaughn Betz, Mahesh A. Iyer, David Z. Pan
2024	—	`conf`	PEARL: Enabling Portable, Productive, and High-Performance Deep Reinforcement Learning using Heterogeneous Platforms. CF Yuan Meng, Michael Kinsner, Deshanand P. Singh, Mahesh A. Iyer, Viktor K. Prasanna
2023	J	`jnl`	A Software-Hardware Co-Optimized Toolkit for Deep Reinforcement Learning on Heterogeneous Platforms. CoRR Yuan Meng, Michael Kinsner, Deshanand P. Singh, Mahesh A. Iyer, Viktor K. Prasanna
2023	—	`conf`	DREAMPlaceFPGA-PL: An Open-Source GPU-Accelerated Packer-Legalizer for Heterogeneous FPGAs. ISPD Rachel Selina Rajarathnam, Zixuan Jiang, Mahesh A. Iyer, David Z. Pan
2022	—	`conf`	DREAMPlaceFPGA: An Open-Source Analytical Placer for Large Scale Heterogeneous FPGAs using Deep-Learning Toolkit. ASP-DAC Rachel Selina Rajarathnam, Mohamed Baker Alawieh, Zixuan Jiang, Mahesh A. Iyer, David Z. Pan
2020	—	`conf`	Agilex™ Generation of Intel® FPGAs. Hot Chips Symposium Ilya K. Ganusov, Mahesh A. Iyer, Ning Cheng, Alon Meisler
2020	—	`conf`	High-Definition Routing Congestion Prediction for Large-Scale FPGAs. ASP-DAC Mohamed Baker Alawieh, Wuxi Li, Yibo Lin, Love Singhal, Mahesh A. Iyer, David Z. Pan
2020	A	`conf`	Symbiosis in Action: Reconfigurable Architectures and EDA. FPGA Mahesh A. Iyer
2019	—	`conf`	A shape-driven spreading algorithm using linear programming for global placement. ASP-DAC Shounak Dhar, Love Singhal, Mahesh A. Iyer, David Z. Pan
2019	B	`conf`	FPGA Accelerated FPGA Placement. FPL Shounak Dhar, Love Singhal, Mahesh A. Iyer, David Z. Pan
2019	—	`conf`	FPGA-Accelerated Spreading for Global Placement. HPEC Shounak Dhar, Love Singhal, Mahesh A. Iyer, David Z. Pan
2017	—	`conf`	An Effective Timing-Driven Detailed Placement Algorithm for FPGAs. ISPD Shounak Dhar, Mahesh A. Iyer, Saurabh N. Adya, Love Singhal, Nikolay Rubanov, David Z. Pan
2017	—	`conf`	CAD Opportunities with Hyper-Pipelining. ISPD Mahesh A. Iyer
2017	A*	`conf`	LSC: A Large-Scale Consensus-Based Clustering Algorithm for High-Performance FPGAs. DAC Love Singhal, Mahesh A. Iyer, Saurabh N. Adya
2016	A	`conf`	Detailed placement for modern FPGAs using 2D dynamic programming. ICCAD Shounak Dhar, Saurabh N. Adya, Love Singhal, Mahesh A. Iyer, David Z. Pan
2009	—	`conf`	On improving optimization effectiveness in interconnect-driven physical synthesis. ISPD Prashant Saxena, Vishal Khandelwal, Changge Qiao, Pei-Hsin Ho, J.-C. Lin, Mahesh A. Iyer
2003	—	`conf`	A Robust and Scalable Technique for the Constraints Solving Problem in High-Level Verification. MTV Mahesh A. Iyer
2003	A	`conf`	Race: A Word-Level ATPG-Based Constraints Solver System For Smart Random Simulation. ITC Mahesh A. Iyer
2000	J	`jnl`	FILL and FUNI: algorithms to identify illegal states and sequentially untestable faults. ACM Trans. Design Autom. Electr. Syst. David E. Long, Mahesh A. Iyer, Miron Abramovici
1999	C	`conf`	A Robust Solution to the Timing Convergence Problem in High-Performance Design. ICCD Narendra V. Shenoy, Mahesh A. Iyer, Robert F. Damiano, Kevin Harer, Hi-Keung Tony Ma, Paul Thilking
1999	A	`conf`	High Time For High Level ATPG. ITC Mahesh A. Iyer
1999	A	`conf`	Wavefront Technology Mapping. DATE Leon Stok, Andrew J. Sullivan, Mahesh A. Iyer
1996	J	`jnl`	FIRE: a fault-independent combinational redundancy identification algorithm. IEEE Trans. Very Large Scale Integr. Syst. Mahesh A. Iyer, Miron Abramovici
1996	A*	`conf`	Identifying Sequential Redundancies Without Search. DAC Mahesh A. Iyer, David E. Long, Miron Abramovici
1996	—	`conf`	Surprises in Sequential Redundancy Identification. ED&TC Mahesh A. Iyer, David E. Long, Miron Abramovici
1995	J	`jnl`	Energy models for delay testing. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Srimat T. Chakradhar, Mahesh A. Iyer, Vishwani D. Agrawal
1995	Misc	`conf`	Identifying sequentially untestable faults using illegal states. VTS David E. Long, Mahesh A. Iyer, Miron Abramovici
1994	Misc	`conf`	Low-Cost Redundancy Identification for Combinatorial Circuits. VLSI Design Mahesh A. Iyer, Miron Abramovici
1994	A	`conf`	Sequentially Untestable Faults Identified Without Search ("Simple Implications Beat Exhaustive Search!"). ITC Mahesh A. Iyer, Miron Abramovici
1992	A	`conf`	One-Pass Redundancy Identification and Removal. ITC Miron Abramovici, Mahesh A. Iyer