Mahendra Sakare

21 papers A 1C 2Misc 2Journal 7Unranked 9
YearRankTypeTitle / Venue / Authors
2025 C conf
A 2.9mW Inverter-based Quadrature Phase Clock Generator with ± 0.29° Phase Error.
ISCAS
Mayank Kumar Singh, M. Bhuvanesh, Rajasekhar Nagulapalli, Devarshi Mrinal Das, Mahendra Sakare
2025 J jnl
SpiMAM: CMOS Implementation of Bio-Inspired Spiking Multidirectional Associative Memory Featuring In-Situ Learning.
IEEE Trans. Circuits Syst. I Regul. Pap.
Sahibia Kaur Vohra, Mahendra Sakare, Alex P. James, Devarshi Mrinal Das
2024 — conf
A 5.4mW 12GHz Quadrature VCO using current reusing technique in 28nm CMOS technology.
ICCCNT
Zahid Rashid Sheikh, Taranveer Kaur, Rajasekhar Nagulapalli, Hitesh Shrimali, Mahendra Sakare
2024 J jnl
Circuit implementation of on-chip trainable spiking neural network using CMOS based memristive STDP synapses and LIF neurons.
Integr.
Sahibia Kaur Vohra, Sherin A. Thomas, Mahendra Sakare, Devarshi Mrinal Das
2023 — conf
A Double Cross-Coupled Delay Cell for High-Frequency Differential Ring VCOs.
APCCAS
Mayank Kumar Singh, Manish Kumar Gautam, Puneet Singh, Rajasekhar Nagulapalli, Devarshi Mrinal Das, Mahendra Sakare
2023 — conf
A Low Power Differential Delay Cell without Cross-Coupled Latch for Ring VCO.
PRIME
Mayank Kumar Singh, Puneet Singh, Devarshi Mrinal Das, Mahendra Sakare
2023 J jnl
A PRBS Generator Using Merged XOR-D Flip-Flop as Building Blocks.
Circuits Syst. Signal Process.
Mayank Kumar Singh, Puneet Singh, Upendra Chichhula, Hirensh Mehra, Devarshi Mrinal Das, Mahendra Sakare
2023 — conf
Analysing Mismatch effect of CMOS Neurons in Spiking Neural Network with Winner-take-all Mechanism.
NorCAS
Sahibia Kaur Vohra, Alex P. James, Mahendra Sakare, Devarshi Mrinal Das
2023 J jnl
Full CMOS Circuit for Brain-Inspired Associative Memory With On-Chip Trainable Memristive STDP Synapse.
IEEE Trans. Very Large Scale Integr. Syst.
Sahibia Kaur Vohra, Sherin A. Thomas, Shivdeep, Mahendra Sakare, Devarshi Mrinal Das
2022 J jnl
CMOS Circuit Implementation of Spiking Neural Network for Pattern Recognition Using On-chip Unsupervised STDP Learning.
CoRR
Sahibia Kaur Vohra, Sherin A. Thomas, Mahendra Sakare, Devarshi Mrinal Das
2021 — conf
A low power 8 × 2
MWSCAS
Mayank Kumar Singh, Puneet Singh, Devarshi Mrinal Das, Mahendra Sakare
2021 — conf
Analytical Modelling of a CMOS Inter Spike Interval Decoder for Resistive Crossbar based Brain Inspired Computing.
VDAT
Sahibia Kaur Vohra, Sherin A. Thomas, Mahendra Sakare, Devarshi Mrinal Das
2021 — conf
Design of a PRBS generator and a serializer using active inductor employed CML latch.
MWSCAS
Puneet Singh, Mayank Kumar Singh, Vinayak Gopal Hande, Mahendra Sakare
2021 — conf
Full CMOS Implementation of Bidirectional Associative Memory Neural Network with Analog Memristive Synapse.
MWSCAS
Sahibia Kaur Vohra, Sherin A. Thomas, Mahendra Sakare, Devarshi Mrinal Das
2017 J jnl
A Power and Area Efficient Architecture of a PRBS Generator With Multiple Outputs.
IEEE Trans. Circuits Syst. II Express Briefs
Mahendra Sakare
2016 Misc conf
A 12.5 Gbps One-Fifth Rate CDR Incorporating a Novel Sampler Based Phase Detector and a DFE.
VLSID
Pragya Maheshwari, Suhas Kaushik, Mahendra Sakare, Shalabh Gupta
2016 Misc conf
A Quarter-Rate 27-1 Pseudo-Random Binary Sequence Generator Using Interleaved Architecture.
VLSID
Mahendra Sakare
2016 J jnl
Bandwidth Enhancement of Flip-Flops Using Feedback for High-Speed Integrated Circuits.
IEEE Trans. Circuits Syst. II Express Briefs
Mahendra Sakare, Sadhu Pavan Kumar, Shalabh Gupta
2014 C conf
A high-speed PRBS generator using flip-flops employing feedback for distributed equalization.
ISCAS
Mahendra Sakare, Shalabh Gupta
2012 — conf
A 4 × 20 Gb/s 29-1 PRBS Generator for Testing a High-Speed DAC in 90nm CMOS Technology.
VDAT
Mahendra Sakare, Mohit Singh, Shalabh Gupta
2011 A conf
Testing of high-speed DACs using PRBS generation with "Alternate-Bit-Tapping".
DATE
Mohit Singh, Mahendra Sakare, Shalabh Gupta