Magnus Själander

89 papers A* 8A 9B 8C 4Misc 3Journal 34Unranked 22
YearRankTypeTitle / Venue / Authors
2026 A conf
PIP: Making Andersen's Points-to Analysis Sound and Practical for Incomplete C Programs.
CGO
Håvard Rognebakke Krogstie, Helge Bahmann, Magnus Själander, Nico Reissmann
2025 — conf
CATBench: A Compiler Autotuning Benchmarking Suite for Black-box Optimization.
AutoML
Jacob O. Tørring, Carl Hvarfner, Luigi Nardi, Magnus Själander
2025 J jnl
HotReRAM: A Performance-Power-Thermal Simulation Framework for ReRAM-Based Caches.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Shounak Chakraborty, Thanasin Bunnam, Jedsada Arunruerk, Sukarn Agarwal, Shengqi Yu, Rishad A. Shafik, Magnus Själander
2025 J jnl
Optimizing Energy Efficiency in Subthreshold RISC-V Cores.
CoRR
Asbjørn Djupdal, Magnus Själander, Magnus Jahre, Snorre Aunet, Trond Ytterdal
2025 J jnl
PIP: Making Andersen's Points-to Analysis Sound and Practical for Incomplete C Programs.
CoRR
Håvard Rognebakke Krogstie, Helge Bahmann, Magnus Själander, Nico Reissmann
2025 J jnl
PRECIOUS: Approximate Real-Time Computing in MLC-MRAM Based Heterogeneous CMPs.
IEEE Trans. Computers
Sangeet Saha, Shounak Chakraborty, Sukarn Agarwal, Magnus Själander, Klaus D. Maier
2025 J jnl
SIRA: Scaled-Integer Range Analysis for Optimizing FPGA Dataflow Neural Network Accelerators.
CoRR
Yaman Umuroglu, Christoph Berganski, Felix Jentzsch, Michal Danilowicz, Tomasz Kryjak, Charalampos Bezaitis, Magnus Själander, Ian Colbert, Thomas B. Preußer, Jakoba Petri-Koenig, Michaela Blott
2025 A* conf
ShadowBinding: Realizing Effective Microarchitectures for In-Core Secure Speculation Schemes.
MICRO
Amund Bergland Kvalsvik, Magnus Själander
2025 J jnl
ShadowBinding: Realizing Effective Microarchitectures for In-Core Secure Speculation Schemes.
CoRR
Amund Bergland Kvalsvik, Magnus Själander
2024 J jnl
ARCTIC: Approximate Real-Time Computing in a Cache-Conscious Multicore Environment.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Sangeet Saha, Shounak Chakraborty, Sukarn Agarwal, Magnus Själander, Klaus D. McDonald-Maier
2024 J jnl
CATBench: A Compiler Autotuning Benchmarking Suite for Black-box Optimization.
CoRR
Jacob O. Tørring, Carl Hvarfner, Luigi Nardi, Magnus Själander
2024 A* conf
MAFin: Maximizing Accuracy in FinFET based Approximated Real-Time Computing.
DAC
Shounak Chakraborty, Sangeet Saha, Magnus Själander, Klaus D. McDonald-Maier
2024 A conf
R-HLS: An IR for Dynamic High-Level Synthesis and Memory Disambiguation based on Regions and State Edges.
ICCAD
David Metz, Nico Reissmann, Magnus Själander
2024 J jnl
R-HLS: An IR for Dynamic High-Level Synthesis and Memory Disambiguation based on Regions and State Edges.
CoRR
David Metz, Nico Reissmann, Magnus Själander
2024 A conf
Sustainable High-Performance Instruction Selection for Superscalar Processors.
ICCAD
Saeideh Sheikhpour, David Metz, Erling Jellum, Magnus Själander, Lieven Eeckhout
2024 A conf
TEEMO: Temperature Aware Energy Efficient Multi-Retention STT-RAM Cache Architecture.
IPDPS
Sukarn Agarwal, Shounak Chakraborty, Magnus Själander
2023 A* conf
Architecting Selective Refresh based Multi-Retention Cache for Heterogeneous System (ARMOUR).
DAC
Sukarn Agarwal, Shounak Chakraborty, Magnus Själander
2023 J jnl
BISDU: A Bit-Serial Dot-Product Unit for Microcontrollers.
ACM Trans. Embed. Comput. Syst.
David Metz, Vineet Kumar, Magnus Själander
2023 J jnl
DELICIOUS: Deadline-Aware Approximate Computing in Cache-Conscious Multicore.
IEEE Trans. Parallel Distributed Syst.
Sangeet Saha, Shounak Chakraborty, Sukarn Agarwal, Rahul Gangopadhyay, Magnus Själander, Klaus D. McDonald-Maier
2023 J jnl
Delay-on-Squash: Stopping Microarchitectural Replay Attacks in Their Tracks.
ACM Trans. Archit. Code Optim.
Christos Sakalis, Stefanos Kaxiras, Magnus Själander
2023 A* conf
Doppelganger Loads: A Safe, Complexity-Effective Optimization for Secure Speculation Schemes.
ISCA
Amund Bergland Kvalsvik, Pavlos Aimoniotis, Stefanos Kaxiras, Magnus Själander
2023 A* conf
ReCon: Efficient Detection, Management, and Use of Non-Speculative Information Leakage.
MICRO
Pavlos Aimoniotis, Amund Bergland Kvalsvik, Xiaoyue Chen, Magnus Själander, Stefanos Kaxiras
2022 — conf
Data-Out Instruction-In (DOIN!): Leveraging Inclusive Caches to Attack Speculative Delay Schemes.
SEED
Pavlos Aimoniotis, Amund Bergland Kvalsvik, Magnus Själander, Stefanos Kaxiras
2022 — conf
STIFF: thermally safe temperature effect inversion aware FinFET based multi-core.
CF
Shounak Chakraborty, Vassos Soteriou, Magnus Själander
2021 J jnl
"It's a Trap!"-How Speculation Invariance Can Be Abused with Forward Speculative Interference.
CoRR
Pavlos Aimoniotis, Christos Sakalis, Magnus Själander, Stefanos Kaxiras
2021 — conf
Do Not Predict - Recompute! How Value Recomputation Can Truly Boost the Performance of Invisible Speculation.
SEED
Christos Sakalis, Zamshed I. Chowdhury, Shayne Wadle, Ismail Akturk, Alberto Ros, Magnus Själander, Stefanos Kaxiras, Ulya R. Karpuzcu
2021 J jnl
On Value Recomputation to Accelerate Invisible Speculation.
CoRR
Christos Sakalis, Zamshed I. Chowdhury, Shayne Wadle, Ismail Akturk, Alberto Ros, Magnus Själander, Stefanos Kaxiras, Ulya R. Karpuzcu
2021 J jnl
Prepare: Power-Aware Approximate Real-time Task Scheduling for Energy-Adaptive QoS Maximization.
ACM Trans. Embed. Comput. Syst.
Shounak Chakraborty, Sangeet Saha, Magnus Själander, Klaus D. McDonald-Maier
2021 J jnl
Reorder Buffer Contention: A Forward Speculative Interference Attack for Speculation Invariant Instructions.
IEEE Comput. Archit. Lett.
Pavlos Aimoniotis, Christos Sakalis, Magnus Själander, Stefanos Kaxiras
2021 — conf
Seeds of SEED: Preventing Priority Inversion in Instruction Scheduling to Disrupt Speculative Interference.
SEED
Christos Sakalis, Magnus Själander, Stefanos Kaxiras
2021 J jnl
Selectively Delaying Instructions to Prevent Microarchitectural Replay Attacks.
CoRR
Christos Sakalis, Stefanos Kaxiras, Magnus Själander
2021 J jnl
WaFFLe: Gated Cache-Ways with Per-Core Fine-Grained DVFS for Reduced On-Chip Temperature and Leakage Consumption.
ACM Trans. Archit. Code Optim.
Shounak Chakraborty, Magnus Själander
2020 B conf
Clearing the Shadows: Recovering Lost Performance for Invisible Speculative Execution through HW/SW Co-Design.
PACT
Kim-Anh Tran, Christos Sakalis, Magnus Själander, Alberto Ros, Stefanos Kaxiras, Alexandra Jimborean
2020 J jnl
Evaluating the Potential Applications of Quaternary Logic for Approximate Computing.
ACM J. Emerg. Technol. Comput. Syst.
Christos Sakalis, Alexandra Jimborean, Stefanos Kaxiras, Magnus Själander
2020 Misc conf
RePAiR: A Strategy for Reducing Peak Temperature while Maximising Accuracy of Approximate Real-Time Computing: Work-in-Progress.
CODES+ISSS
Shounak Chakraborty, Sangeet Saha, Magnus Själander, Klaus D. McDonald-Maier
2020 A* conf
Twig: Multi-Agent Task Management for Colocated Latency-Critical Cloud Services.
HPCA
Rajiv Nishtala, Vinicius Petrucci, Paul M. Carpenter, Magnus Själander
2020 J jnl
Understanding Selective Delay as a Method for Efficient Secure Speculative Execution.
IEEE Trans. Computers
Christos Sakalis, Stefanos Kaxiras, Alberto Ros, Alexandra Jimborean, Magnus Själander
2019 J jnl
EPIC: An Energy-Efficient, High-Performance GPGPU Computing Research Infrastructure.
CoRR
Magnus Själander, Magnus Jahre, Gunnar Tufte, Nico Reissmann
2019 A* conf
Efficient invisible speculative execution through selective delay and value prediction.
ISCA
Christos Sakalis, Stefanos Kaxiras, Alberto Ros, Alexandra Jimborean, Magnus Själander
2019 — conf
Ghost loads: what is the cost of invisible speculation?
CF
Christos Sakalis, Mehdi Alipour, Alberto Ros, Alexandra Jimborean, Stefanos Kaxiras, Magnus Själander
2019 — conf
Improving Memory Access Locality for Vectorized Bit-Serial Matrix Multiplication in Reconfigurable Computing.
FPT
Lahiru Rasnayake, Magnus Själander
2019 J jnl
Optimizing Bit-Serial Matrix Multiplication for Reconfigurable Computing.
CoRR
Yaman Umuroglu, Davide Conficconi, Lahiru Rasnayake, Thomas B. Preußer, Magnus Själander
2019 J jnl
Optimizing Bit-Serial Matrix Multiplication for Reconfigurable Computing.
ACM Trans. Reconfigurable Technol. Syst.
Yaman Umuroglu, Davide Conficconi, Lahiru Rasnayake, Thomas B. Preußer, Magnus Själander
2019 J jnl
RVSDG: An Intermediate Representation for Optimizing Compilers.
CoRR
Nico Reissmann, Jan Christian Meyer, Helge Bahmann, Magnus Själander
2018 B conf
BISMO: A Scalable Bit-Serial Matrix Multiplication Overlay for Reconfigurable Computing.
FPL
Yaman Umuroglu, Lahiru Rasnayake, Magnus Själander
2018 J jnl
BISMO: A Scalable Bit-Serial Matrix Multiplication Overlay for Reconfigurable Computing.
CoRR
Yaman Umuroglu, Lahiru Rasnayake, Magnus Själander
2018 A* conf
SWOOP: software-hardware co-design for non-speculative, execute-ahead, in-order cores.
PLDI
Kim-Anh Tran, Alexandra Jimborean, Trevor E. Carlson, Konstantinos Koukos, Magnus Själander, Stefanos Kaxiras
2018 J jnl
Static Instruction Scheduling for High Performance on Limited Hardware.
IEEE Trans. Computers
Kim-Anh Tran, Trevor E. Carlson, Konstantinos Koukos, Magnus Själander, Vasileios Spiliopoulos, Stefanos Kaxiras, Alexandra Jimborean
2017 A conf
Clairvoyance: look-ahead compile-time scheduling.
CGO
Kim-Anh Tran, Trevor E. Carlson, Konstantinos Koukos, Magnus Själander, Vasileios Spiliopoulos, Stefanos Kaxiras, Alexandra Jimborean
2017 J jnl
Transcending Hardware Limits with Software Out-of-Order Processing.
IEEE Comput. Archit. Lett.
Trevor E. Carlson, Kim-Anh Tran, Alexandra Jimborean, Konstantinos Koukos, Magnus Själander, Stefanos Kaxiras
2016 B conf
Poster: Approximation: A New Paradigm also for Wireless Sensing.
EWSN
Thiemo Voigt, Magnus Själander, Frederik Hermans
2016 A conf
Practical way halting by speculatively accessing halt tags.
DATE
Daniel Moreau, Alen Bardizbanyan, Magnus Själander, David B. Whalley, Per Larsson-Edefors
2016 Misc conf
Redesigning a tagless access buffer to require minimal ISA changes.
CASES
Carlos Sanchez, Peter Gavin, Daniel Moreau, Magnus Själander, David B. Whalley, Per Larsson-Edefors, Sally A. McKee
2016 — conf
Techniques for modulating error resilience in emerging multi-value technologies.
Conf. Computing Frontiers
Magnus Själander, Gustaf Borgström, Mykhailo V. Klymenko, Françoise Remacle, Stefanos Kaxiras
2015 B conf
Improving Data Access Efficiency by Using Context-Aware Loads and Stores.
LCTES
Alen Bardizbanyan, Magnus Själander, David B. Whalley, Per Larsson-Edefors
2015 B conf
Optimizing Transfers of Control in the Static Pipeline Architecture.
LCTES
Ryan Baird, Peter Gavin, Magnus Själander, David B. Whalley, Gang-Ryung Uh
2015 Misc conf
Scheduling instruction effects for a statically pipelined processor.
CASES
B. Davis, Ryan Baird, Peter Gavin, Magnus Själander, Ian Finlayson, F. Rasapour, G. Cook, Gang-Ryung Uh, David B. Whalley, Gary S. Tyson
2014 — conf
A tunable cache for approximate computing.
NANOARCH
Magnus Själander, Nina Shariati Nilsson, Stefanos Kaxiras
2014 — book
Power-Efficient Computer Architectures: Recent Advances
Power-Efficient Computer Architectures
Magnus Själander, Margaret Martonosi, Stefanos Kaxiras
2014 A conf
Reducing set-associative L1 data cache energy by early load data dependence detection (ELD
DATE
Alen Bardizbanyan, Magnus Själander, David B. Whalley, Per Larsson-Edefors
2013 J jnl
Designing a practical data filter cache to improve both energy efficiency and performance.
ACM Trans. Archit. Code Optim.
Alen Bardizbanyan, Magnus Själander, David B. Whalley, Per Larsson-Edefors
2013 — conf
FlexCore: Implementing an exposed datapath processor.
ICSAMOS
Magnus Själander, Per Larsson-Edefors
2013 A conf
Improving data access efficiency by using a tagless access buffer (TAB).
CGO
Alen Bardizbanyan, Peter Gavin, David B. Whalley, Magnus Själander, Per Larsson-Edefors, Sally A. McKee, Per Stenström
2013 B conf
Improving processor efficiency by statically pipelining instructions.
LCTES
Ian Finlayson, Brandon Davis, Peter Gavin, Gang-Ryung Uh, David B. Whalley, Magnus Själander, Gary S. Tyson
2013 J jnl
Reducing instruction fetch energy in multi-issue processors.
ACM Trans. Archit. Code Optim.
Peter Gavin, David B. Whalley, Magnus Själander
2013 C conf
Speculative tag access for reduced energy dissipation in set-associative L1 data caches.
ICCD
Alen Bardizbanyan, Magnus Själander, David B. Whalley, Per Larsson-Edefors
2012 B conf
An LTE Uplink Receiver PHY benchmark and subframe-based power management.
ISPASS
Magnus Själander, Sally A. McKee, Peter Brauer, David Engdal, András Vajda
2012 — conf
Configurable RTL model for level-1 caches.
NORCHIP
Vahid Saljooghi, Alen Bardizbanyan, Magnus Själander, Per Larsson-Edefors
2012 J jnl
Techniques to Measure, Model, and Manage Power.
Adv. Comput.
Bhavishya Goel, Sally A. McKee, Magnus Själander
2012 — conf
Viterbi Accelerator for Embedded Processor Datapaths.
ASAP
Muhammad Waqar Azhar, Magnus Själander, Hasan Ali, Akshay Vijayashekar, Tung Thanh Hoang, Kashan Khurshid Ansari, Per Larsson-Edefors
2011 B conf
Power-Aware Resource Scheduling in Base Stations.
MASCOTS
Magnus Själander, Sally A. McKee, Bhavishya Goel, Peter Brauer, David Engdal, András Vajda
2011 — conf
Reconfigurable Instruction Decoding for a Wide-Control-Word Processor.
IPDPS Workshops
Alen Bardizbanyan, Magnus Själander, Per Larsson-Edefors
2010 J jnl
A High-Speed, Energy-Efficient Two-Cycle Multiply-Accumulate (MAC) Architecture and Its Application to a Double-Throughput MAC Unit.
IEEE Trans. Circuits Syst. I Regul. Pap.
Tung Thanh Hoang, Magnus Själander, Per Larsson-Edefors
2010 — conf
Design space exploration for an embedded processor with flexible datapath interconnect.
ASAP
Tung Thanh Hoang, Ulf Jalmbrant, Erik der Hagopian, Kasyab P. Subramaniyan, Magnus Själander, Per Larsson-Edefors
2009 — conf
A Flexible Code Compression Scheme Using Partitioned Look-Up Tables.
HiPEAC
Martin Thuresson, Magnus Själander, Per Stenström
2009 — conf
Custom layout strategy for rectangle-shaped log-depth multiplier reduction tree.
ICECS
Patrik Kimfors, Niklas Broman, Andreas Haraldsson, Kasyab P. Subramaniyan, Magnus Själander, Henrik Eriksson, Per Larsson-Edefors
2009 A conf
Double Throughput Multiply-Accumulate unit for FlexCore processor enhancements.
IPDPS
Tung Thanh Hoang, Magnus Själander, Per Larsson-Edefors
2009 J jnl
FlexCore: Utilizing Exposed Datapath Control for Efficient Computing.
J. Signal Process. Syst.
Martin Thuresson, Magnus Själander, Magnus Björk, Lars J. Svensson, Per Larsson-Edefors, Per Stenström
2009 — conf
High-speed, energy-efficient 2-cycle Multiply-Accumulate architecture.
SoCC
Tung Thanh Hoang, Magnus Själander, Per Larsson-Edefors
2009 J jnl
Multiplication Acceleration Through Twin Precision.
IEEE Trans. Very Large Scale Integr. Syst.
Magnus Själander, Per Larsson-Edefors
2009 — conf
Scheduling for an Embedded Architecture with a Flexible Datapath.
ISVLSI
Thomas Schilling, Magnus Själander, Per Larsson-Edefors
2008 C conf
A Look-Ahead Task Management Unit for Embedded Multi-Core Architectures.
DSD
Magnus Själander, Andrei Sergeevich Terechko, Marc Duranton
2008 J jnl
Early detection and bypassing of trivial operations to improve energy efficiency of processors.
Microprocess. Microsystems
Md. Mafijul Islam, Magnus Själander, Per Stenström
2008 — conf
High-speed and low-power multipliers using the Baugh-Wooley algorithm and HPM reduction tree.
ICECS
Magnus Själander, Per Larsson-Edefors
2007 — conf
A Flexible Datapath Interconnect for Embedded Applications.
ISVLSI
Magnus Själander, Per Larsson-Edefors, Magnus Björk
2007 — conf
FlexCore: Utilizing Exposed Datapath Control for Efficient Computing.
ICSAMOS
Martin Thuresson, Magnus Själander, Magnus Björk, Lars J. Svensson, Per Larsson-Edefors, Per Stenström
2006 C conf
Multiplier reduction tree with logarithmic logic depth and regular connectivity.
ISCAS
Henrik Eriksson, Per Larsson-Edefors, Mary Sheeran, Magnus Själander, Daniel Johansson, Martin Scholin
2005 — conf
A low-leakage twin-precision multiplier using reconfigurable power gating.
ISCAS (2)
Magnus Själander, Mindaugas Drazdziulis, Per Larsson-Edefors, Henrik Eriksson
2004 C conf
An Efficient Twin-Precision Multiplier.
ICCD
Magnus Själander, Henrik Eriksson, Per Larsson-Edefors