Maged Ghoneima

58 papers A* 2A 4C 12Journal 13Unranked 27

Year	Rank	Type	Title / Venue / Authors
2020	—	`conf`	Reconfigurable Systolic-based Pyramidal Neuron Block for CNN Acceleration on FPGA. ICSET Hossam O. Ahmed, Maged Ghoneima, Mohamed Dessouky
2019	J	`jnl`	Systolic-based pyramidal neuron accelerator blocks for convolutional neural network. Microelectron. J. Hossam O. Ahmed, Maged Ghoneima, Mohamed Dessouky
2018	J	`jnl`	Design and analysis of 2T2M hybrid CMOS-Memristor based RRAM. Microelectron. J. Noha Shaarawy, Ahmed A. M. Emara, Ahmed M. El-Naggar, Mohammed E. Elbtity, Maged Ghoneima, Ahmed G. Radwan
2018	—	`conf`	High-Speed 2D Parallel MAC Unit Hardware Accelerator for Convolutional Neural Network. IntelliSys (1) Hossam O. Ahmed, Maged Ghoneima, Mohamed Dessouky
2018	—	`conf`	Pyramidal Neuron Architectures for AcceleratingDeep Neural Networks on FPGA. AHS Hossam O. Ahmed, Maged Ghoneima, Mohamed Dessouky
2018	—	`conf`	Real-Time Car Detection-Based Depth Estimation Using Mono Camera. ICM I. Mohamed Elzayat, M. Ahmed Saad, M. Mohamed Mostafa, R. Mahmoud Hassan, Hossam Abd El Munim, Maged Ghoneima, M. Saeed Darweesh, Hassan Mostafa
2018	—	`conf`	Real-Time Lane Detection-Based Line Segment Detection. NGCAS Ahmed Mahmoud, Loay Ehab, Mohamed Reda, Mostafa Abdelaleem, Hossam Abd El Munim, Maged Ghoneima, M. Saeed Darweesh, Hassan Mostafa
2017	—	`conf`	Metaheuristic optimization in path planning of autonomous vehicles under the ATOM framework. ICVES Youmna Magdy, Omar M. Shehata, Mohamed Abdelaziz, Maged Ghoneima, Farid A. Tolbah
2017	J	`jnl`	PASSIOT: A Pareto-optimal multi-objective optimization approach for synthesis of analog circuits using Sobol' indices-based engine. Integr. Taher Kourany, Maged Ghoneima, Emad Hegazi, Yehea Ismail
2016	C	`conf`	A fast locking hybrid TDC-BB ADPLL utilizing proportional derivative digital loop filter and power gated DCO. ISCAS Amr Lotfy, Maged Ghoneima, Mohamed Abdel-Moneum
2016	—	`conf`	A fixed function 3D rendering hardware for mobile applications. ICM Eslam Khafagy, Ahmed Hatab, Amr Rashed, Ahmed A. M. Emara, Maged Ghoneima
2016	—	`conf`	Modeling and analysis of stretching strain in clamped-clamped beams for energy harvesting. MWSCAS Ahmed Emad, Mohamed A. E. Mahmoud, Maged Ghoneima, Mohamed Dessouky
2016	—	`conf`	Optimization of the output power of a frequency-up conversion piezoelectric energy harvester. MWSCAS Mostafa Shadoufa, Mohamed Mahmoud, Maged Ghoneima, Mohamed Dessouky
2016	—	`conf`	PASSIOT: A pareto-optimal multi-objective optimization approach for synthesis of analog circuits using sobol' indices-based engine. MWSCAS Taher Kourany, Maged Ghoneima, Emad Hegazi, Yehea Ismail
2016	A*	`conf`	Sperm-shaped magnetic microrobots: Fabrication using electrospinning, modeling, and characterization. ICRA Islam S. M. Khalil, Ahmet Fatih Tabak, Abdelrahman Hosney, Abdallah Mohamed, Anke Klingner, Maged Ghoneima, Metin Sitti
2016	J	`jnl`	Tile-Based Modular Architecture for Accelerating Homomorphic Function Evaluation on FPGA. IACR Cryptol. ePrint Arch. Mustafa Khairallah, Maged Ghoneima
2016	—	`conf`	Tile-based modular architecture for accelerating homomorphic function evaluation on FPGA. MWSCAS Mustafa Khairallah, Maged Ghoneima
2015	C	`conf`	2T2M memristor-based memory cell for higher stability RRAM modules. ISCAS Noha Shaarawy, Maged Ghoneima, Ahmed G. Radwan
2015	—	`conf`	A 24 Gbps SerDes transceiver for on-chip networks using a new half-data-rate self-timed 3-level signaling scheme. ICEAC Ramy N. Tadros, Ahmed H. Abdelrahman, Maged Ghoneima, Yehea Ismail
2015	—	`conf`	A reference-less multilevel memristor based RRAM module. MWSCAS Ahmed A. M. Emara, Maged Ghoneima
2015	C	`conf`	New polynomial basis versatile multiplier over GF(2 ISCAS Mustafa Khairallah, Maged Ghoneima
2015	—	`conf`	Structure optimization for efficient AlN piezoelectric energy harvesters. ICECS Mostafa Shadoufa, Ahmed Emad, Maged Ghoneima, Mohamed A. E. Mahmoud, Mohamed Dessouky
2014	C	`conf`	A variation tolerant driving technique for all-digital self-timed 3-level signaling high-speed SerDes transceivers for on-chip networks. ISCAS Ramy N. Tadros, Abdelrahman H. Elsayed, Maged Ghoneima, Yehea I. Ismail
2014	C	`conf`	Low-power all-digital manchester-encoding-based high-speed serdes transceiver for on-chip networks. ISCAS Abdelrahman H. Elsayed, Ramy N. Tadros, Maged Ghoneima, Yehea I. Ismail
2012	C	`conf`	A 0.8V 6.4µW compact mixed-signal front-end for neural implants. ISCAS Ahmed El Kholy, Maged Ghoneima, Khaled Sharaf
2012	C	`conf`	A 16Gbps low power self-timed SerDes transceiver for multi-core communication. ISCAS Ezz El-Din O. Hussein, Sally Safwat, Maged Ghoneima, Yehea I. Ismail
2012	C	`conf`	A 5-10GHz low power bang-bang all digital PLL based on programmable digital loop filter. ISCAS Sally Safwat, Amr Lotfy, Maged Ghoneima, Yehea I. Ismail
2012	—	`conf`	A novel digital loop filter architecture for bang-bang ADPLL. SoCC Moataz Abdelfattah, Maged Ghoneima, Yehea I. Ismail, Amr Lotfy, Mohamed Abdelsalam, Mohamed Abdel-Moneum, Nasser A. Kurd, Greg Taylor
2012	—	`conf`	Modeling the response of Bang-Bang digital PLLs to phase error perturbations. CICC Moataz Abdelfattah, Maged Ghoneima, Yehea I. Ismail, Amr Lotfy, Mohamed Abdel-Moneum, Nasser A. Kurd, Greg Taylor
2011	C	`conf`	A 12Gbps all digital low power SerDes transceiver for on-chip networking. ISCAS Sally Safwat, Ezz El-Din O. Hussein, Maged Ghoneima, Yehea I. Ismail
2011	—	`conf`	A design methodology for a low power bang-bang all digital PLL based on digital loop filter programmable coefficients. ICEAC Sally Safwat, Maged Ghoneima, Yehea I. Ismail
2011	C	`conf`	A dynamic calibration scheme for on-chip process and temperature variations. ISCAS Mina Raymond, Maged Ghoneima, Yehea I. Ismail
2011	—	`conf`	A novel power gated digitally controlled oscillator. ICEAC Amr M. Lotfy, Maged Ghoneima, Mohamed Abdel-Moneum
2011	J	`jnl`	Guest Editorial Special Issue on ISCAS 2010. IEEE Trans. Circuits Syst. I Regul. Pap. Maged Ghoneima, Yong Lian, Gabriele Manganaro, Shahriar Mirabbasi, Christian Piguet, Wouter A. Serdijn
2009	J	`jnl`	SSMCB: Low-Power Variation-Tolerant Source-Synchronous Multicycle Bus. IEEE Trans. Circuits Syst. I Regul. Pap. Maged Ghoneima, Yehea I. Ismail, Muhammad M. Khellah, Vivek De
2009	J	`jnl`	Serial-Link Bus: A Low-Power On-Chip Bus Architecture. IEEE Trans. Circuits Syst. I Regul. Pap. Maged Ghoneima, Yehea I. Ismail, Muhammad M. Khellah, James W. Tschanz, Vivek De
2008	J	`jnl`	Skewed Repeater Bus: A Low-Power Scheme for On-Chip Buses. IEEE Trans. Circuits Syst. I Regul. Pap. Maged Ghoneima, Muhammad M. Khellah, James W. Tschanz, Yibin Ye, Nasser A. Kurd, Javed Barkatullah, Srikanth Nimmagadda, Yehea I. Ismail, Vivek K. De
2007	J	`jnl`	Variation-Tolerant and Low-Power Source-Synchronous Multicycle On-Chip Interconnect Scheme. VLSI Design Maged Ghoneima, Yehea I. Ismail, Muhammad M. Khellah, Vivek De
2006	J	`jnl`	Formal derivation of optimal active shielding for low-power on-chip buses. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Maged Ghoneima, Yehea I. Ismail, Muhammad M. Khellah, James W. Tschanz, Vivek De
2006	—	`conf`	Reducing the Data Switching Activity on Serial Link Buses. ISQED Maged Ghoneima, Yehea I. Ismail, Muhammad M. Khellah, Vivek De
2006	J	`jnl`	Reducing the Effective Coupling Capacitance in Buses Using Threshold Voltage Adjustment Techniques. IEEE Trans. Circuits Syst. I Regul. Pap. Maged Ghoneima, Yehea I. Ismail, Muhammad M. Khellah, James W. Tschanz, Vivek De
2006	C	`conf`	Reducing the data switching activity of serialized datastreams. ISCAS Maged Ghoneima, Yehea I. Ismail, Muhammad M. Khellah, Vivek De
2006	A	`conf`	Time-borrowing multi-cycle on-chip interconnects for delay variation tolerance. ISLPED Keith A. Bowman, James W. Tschanz, Muhammad M. Khellah, Maged Ghoneima, Yehea I. Ismail, Vivek De
2005	C	`conf`	A Skewed Repeater Bus Architecture for On-Chip Energy Reduction in Microprocessors. ICCD Muhammad M. Khellah, Maged Ghoneima, James W. Tschanz, Yibin Ye, Nasser A. Kurd, Javed Barkatullah, Srikanth Nimmagadda, Yehea I. Ismail
2005	—	`conf`	Accurate decoupling of capacitively coupled buses. ISCAS (4) Maged Ghoneima, Yehea I. Ismail
2005	—	`conf`	Low-power prediction based data transfer architecture. CICC Maged Ghoneima, Ehsan Atoofian, Amirali Baniasadi, Yehea I. Ismail
2005	J	`jnl`	Optimum positioning of interleaved repeaters in bidirectional buses. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Maged Ghoneima, Yehea I. Ismail
2005	—	`conf`	Physical limitations on the bit-rate of on-chip interconnects. ACM Great Lakes Symposium on VLSI Noha H. Mahmoud, Maged Ghoneima, Yehea I. Ismail
2005	A	`conf`	Serial-link bus: a low-power on-chip bus architecture. ICCAD Maged Ghoneima, Yehea I. Ismail, Muhammad M. Khellah, James W. Tschanz, Vivek De
2005	—	`conf`	Skewing adjacent line repeaters to reduce the delay and energy dissipation of on-chip buses. ISCAS (1) Yehea I. Ismail, Muhammad M. Khellah, Maged Ghoneima, James W. Tschanz, Yibin Ye, Vivek De
2005	—	`conf`	The importance of including thermal effects in estimating the effectiveness of power reduction techniques. CICC Ja Chun Ku, Maged Ghoneima, Yehea I. Ismail
2004	A	`conf`	Delayed line bus scheme: a low-power bus scheme for coupled on-chip buses. ISLPED Maged Ghoneima, Yehea I. Ismail
2004	—	`conf`	Effect of relative delay on the dissipated energy in coupled interconnects. ISCAS (2) Maged Ghoneima, Yehea I. Ismail
2004	A	`conf`	Formal derivation of optimal active shielding for low-power on-chip buses. ICCAD Maged Ghoneima, Yehea I. Ismail
2004	—	`conf`	Low power coupling-based encoding for on-chip buses. ISCAS (2) Maged Ghoneima, Yehea I. Ismail
2004	—	`conf`	Low-power on-chip bus architecture using dynamic relative delays. SoCC Maged Ghoneima, Yehea I. Ismail
2004	J	`jnl`	Utilizing the effect of relative delay on energy dissipation in low-power on-chip buses. IEEE Trans. Very Large Scale Integr. Syst. Maged Ghoneima, Yehea I. Ismail
2003	A*	`conf`	Optimum positioning of interleaved repeaters In bidirectional buses. DAC Maged Ghoneima, Yehea I. Ismail