Magdy S. Abadir

155 papers A* 14A 36C 4Misc 14Journal 44Unranked 38

Year	Rank	Type	Title / Venue / Authors
2019	J	`jnl`	Editorial TVLSI Positioning - Continuing and Accelerating an Upward Trajectory. IEEE Trans. Very Large Scale Integr. Syst. Massimo Alioto, Magdy S. Abadir, Tughrul Arslan, Chirn Chye Boon, Andreas Burg, Chip-Hong Chang, Meng-Fan Chang, Yao-Wen Chang, Poki Chen, Pasquale Corsonello, Paolo Crovetti, Shiro Dosho, Rolf Drechsler, Ibrahim Abe M. Elfadel, Ruonan Han, Masanori Hashimoto, Chun-Huat Heng, Deukhyoun Heo, Tsung-Yi Ho, Houman Homayoun, Yuh-Shyan Hwang, Ajay Joshi, Rajiv V. Joshi, Tanay Karnik, Chulwoo Kim, Tony Tae-Hyoung Kim, Jaydeep P. Kulkarni, Volkan Kursun, Yoonmyung Lee, Hai Helen Li, Huawei Li, Prabhat Mishra, Baker Mohammad, Mehran Mozaffari Kermani, Makoto Nagata, Koji Nii, Partha Pratim Pande, Bipul C. Paul, Vasilis F. Pavlidis, José Pineda de Gyvez, Ioannis Savidis, Patrick Schaumont, Fabio Sebastiano, Anirban Sengupta, Mingoo Seok, Mircea R. Stan, Mark Tehranipoor, Aida Todri-Sanial, Marian Verhelst, Valerio Vignoli, Xiaoqing Wen, Jiang Xu, Wei Zhang, Zhengya Zhang, Jun Zhou, Mark Zwolinski, Stacey Weber
2017	J	`jnl`	Challenges and Trends in Modern SoC Design Verification. IEEE Des. Test Wen Chen, Sandip Ray, Jayanta Bhadra, Magdy S. Abadir, Li-C. Wang
2017	J	`jnl`	Guest Editors' Introduction: Emerging Challenges and Solutions in SoC Verification. IEEE Des. Test Magdy S. Abadir, Jayanta Bhadra, Wen Chen, Li-C. Wang
2014	A*	`conf`	Data Mining In EDA - Basic Principles, Promises, and Constraints. DAC Li-C. Wang, Magdy S. Abadir
2014	C	`conf`	Multivariate outlier modeling for capturing customer returns - How simple it can be. IOLTS Jeff Tikkanen, Nik Sumikawa, Li-C. Wang, Magdy S. Abadir
2014	A	`conf`	Yield optimization using advanced statistical correlation methods. ITC Jeff Tikkanen, Sebastian Siatkowski, Nik Sumikawa, Li-C. Wang, Magdy S. Abadir
2013	A	`conf`	A pattern mining framework for inter-wafer abnormality analysis. ITC Nik Sumikawa, Li-C. Wang, Magdy S. Abadir
2013	J	`jnl`	Guest Editorial: Test and Verification Challenges for Future Microprocessors and SoC Designs. J. Electron. Test. Sandip Ray, Jay Bhadra, Magdy S. Abadir, Li-C. Wang
2013	C	`conf`	Keynote 1 - VLSI 2.0: R&D Post Moore. VLSI-SoC Sani R. Nassif, Yale N. Patt, Magdy S. Abadir
2013	—	`conf`	Novel test analysis to improve structural coverage - A commercial experiment. VLSI-DAT Wen Chen, Li-C. Wang, Jayanta Bhadra, Magdy S. Abadir
2013	A*	`conf`	Simulation knowledge extraction and reuse in constrained random processor verification. DAC Wen Chen, Li-C. Wang, Jay Bhadra, Magdy S. Abadir
2012	A	`conf`	An experiment of burn-in time reduction based on parametric test analysis. ITC Nik Sumikawa, Li-C. Wang, Magdy S. Abadir
2012	—	`conf`	Data mining based prediction paradigm and its applications in design automation. VLSI-DAT Magdy S. Abadir, Nik Sumikawa, Wen Chen, Li-C. Wang
2012	J	`jnl`	Introduction to special section on verification challenges in the concurrent world. ACM Trans. Design Autom. Electr. Syst. Sandip Ray, Jayanta Bhadra, Magdy S. Abadir, Li-C. Wang, Aarti Gupta
2012	A	`conf`	Novel test detection to improve simulation efficiency - A commercial experiment. ICCAD Wen Chen, Nik Sumikawa, Li-C. Wang, Jayanta Bhadra, Xiushan Feng, Magdy S. Abadir
2012	A	`conf`	Screening customer returns with multivariate test analysis. ITC Nik Sumikawa, Jeff Tikkanen, Li-C. Wang, LeRoy Winemberg, Magdy S. Abadir
2011	—	`ed.`	12th International Workshop on Microprocessor Test and Verification, MTV 2011, Austin, TX, USA, December 5-7, 2011 MTV Magdy S. Abadir, Jay Bhadra, Li-C. Wang
2011	A	`conf`	Forward prediction based on wafer sort data - A case study. ITC Nik Sumikawa, Dragoljub Gagi Drmanac, Li-C. Wang, LeRoy Winemberg, Magdy S. Abadir
2011	A	`conf`	Multidimensional parametric test set optimization of wafer probe data for predicting in field failures and setting tighter test limits. DATE Dragoljub Gagi Drmanac, Nik Sumikawa, LeRoy Winemberg, Li-C. Wang, Magdy S. Abadir
2011	Misc	`conf`	Understanding customer returns from a test perspective. VTS Nik Sumikawa, Dragoljub Gagi Drmanac, Li-C. Wang, LeRoy Winemberg, Magdy S. Abadir
2010	—	`ed.`	11th International Workshop on Microprocessor Test and Verification, MTV 2010, Austin, TX, USA, December 13-15, 2010 MTV Magdy S. Abadir, Jay Bhadra, Li-C. Wang
2010	A*	`conf`	Classification rule learning using subgroup discovery of cross-domain attributes responsible for design-silicon mismatch. DAC Nicholas Callegari, Dragoljub Gagi Drmanac, Li-C. Wang, Magdy S. Abadir
2010	—	`conf`	Coverage metrics for verification of concurrent SystemC designs using mutation testing. HLDVT Alper Sen, Magdy S. Abadir
2010	—	`conf`	Design for reality: knowledge discovery in design and test data. SBCCI Magdy S. Abadir
2010	J	`jnl`	Feature-Ranking Methodology to Diagnose Design-Silicon Timing Mismatch. IEEE Des. Test Comput. Pouria Bastani, Nicholas Callegari, Li-C. Wang, Magdy S. Abadir
2009	J	`jnl`	A Statistical Diagnosis Approach for Analyzing Design-Silicon Timing Mismatch. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Nicholas Callegari, Pouria Bastani, Li-C. Wang, Magdy S. Abadir
2009	A	`conf`	Minimizing outlier delay test cost in the presence of systematic variability. ITC Dragoljub Gagi Drmanac, Brendon Bolin, Li-C. Wang, Magdy S. Abadir
2009	A	`conf`	TRAM: A tool for Temperature and Reliability Aware Memory Design. DATE Amin Khajeh, Aseem Gupta, Nikil D. Dutt, Fadi J. Kurdahi, Ahmed M. Eltawil, Kamal S. Khouri, Magdy S. Abadir
2008	A	`conf`	Diagnosis of design-silicon timing mismatch with feature encoding and importance ranking - the methodology explained. ITC Pouria Bastani, Nicholas Callegari, Li-C. Wang, Magdy S. Abadir
2008	J	`jnl`	Linking Statistical Learning to Diagnosis. IEEE Des. Test Comput. Pouria Bastani, Li-C. Wang, Magdy S. Abadir
2008	A*	`conf`	Predictive runtime verification of multi-processor SoCs in SystemC. DAC Alper Sen, Vinit Ogale, Magdy S. Abadir
2008	A*	`conf`	Statistical diagnosis of unmodeled systematic timing effects. DAC Pouria Bastani, Nicholas Callegari, Li-C. Wang, Magdy S. Abadir
2008	—	`conf`	Thermal Aware Global Routing of VLSI Chips for Enhanced Reliability. ISQED Aseem Gupta, Nikil D. Dutt, Fadi J. Kurdahi, Kamal S. Khouri, Magdy S. Abadir
2008	J	`jnl`	Validating Power Architecture IEEE Trans. Very Large Scale Integr. Syst. Jayanta Bhadra, Ekaterina Trofimova, Magdy S. Abadir
2007	J	`jnl`	A Survey of Hybrid Techniques for Functional Verification. IEEE Des. Test Comput. Jayanta Bhadra, Magdy S. Abadir, Li-C. Wang, Sandip Ray
2007	A	`conf`	Analyzing the risk of timing modeling based on path delay tests. ITC Pouria Bastani, Benjamin N. Lee, Li-C. Wang, Savithri Sundareswaran, Magdy S. Abadir
2007	A*	`conf`	Design-Silicon Timing Correlation A Data Mining Perspective. DAC Li-C. Wang, Pouria Bastani, Magdy S. Abadir
2007	—	`ed.`	Eighth International Workshop on Microprocessor Test and Verification (MTV 2007), Common Challenges and Solutions, 5-6 December 2007, Austin, Texas, USA MTV Magdy S. Abadir, Li-C. Wang, Jayanta Bhadra
2007	J	`jnl`	Guest Editors' Introduction: Attacking Functional Verification through Hybrid Techniques. IEEE Des. Test Comput. Jayanta Bhadra, Magdy S. Abadir, Li-C. Wang
2007	—	`conf`	LEAF: A System Level Leakage-Aware Floorplanner for SoCs. ASP-DAC Aseem Gupta, Nikil D. Dutt, Fadi J. Kurdahi, Kamal S. Khouri, Magdy S. Abadir
2007	A	`conf`	Maximum circuit activity estimation using pseudo-boolean satisfiability. DATE Hratch Mangassarian, Andreas G. Veneris, Sean Safarpour, Farid N. Najm, Magdy S. Abadir
2007	Misc	`conf`	STEFAL: A System Level Temperature- and Floorplan-Aware Leakage Power Estimator for SoCs. VLSI Design Aseem Gupta, Nikil D. Dutt, Fadi J. Kurdahi, Kamal S. Khouri, Magdy S. Abadir
2007	A	`conf`	Statistical analysis and optimization of parametric delay test. ITC Sean Hsi Yuan Wu, Benjamin N. Lee, Li-C. Wang, Magdy S. Abadir
2006	—	`conf`	A Trace-Driven Validation Methodology for Multi-Processor SOCS. SoCC Jayanta Bhadra, Ekaterina Trofimova, Leonard J. Giordano, Magdy S. Abadir
2006	—	`conf`	Directed Micro-architectural Test Generation for an Industrial Processor: A Case Study. MTV Heon-Mo Koo, Prabhat Mishra, Jayanta Bhadra, Magdy S. Abadir
2006	—	`conf`	Extracting a Simplified View of Design Functionality Based on Vector Simulation. Haifa Verification Conference Onur Guzey, Charles H.-P. Wen, Li-C. Wang, Tao Feng, Hillel Miller, Magdy S. Abadir
2006	—	`conf`	Extracting a simplified view of design functionality via vector simulation. HLDVT Onur Guzey, Charles H.-P. Wen, Li-C. Wang, Tao Feng, Magdy S. Abadir
2006	Misc	`conf`	Floorplan driven leakage power aware IP-based SoC design space exploration. CODES+ISSS Aseem Gupta, Nikil D. Dutt, Fadi J. Kurdahi, Kamal S. Khouri, Magdy S. Abadir
2006	C	`conf`	Floorplanning and Thermal Impact on Leakage Power and Proper Operation of Complex SOC Designs. IOLTS Magdy S. Abadir
2006	A	`conf`	Issues on Test Optimization with Known Good Dies and Known Defective Dies - A Statistical Perspective. ITC Benjamin N. Lee, Li-C. Wang, Magdy S. Abadir
2006	A*	`conf`	Refined statistical static timing analysis through. DAC Benjamin N. Lee, Li-C. Wang, Magdy S. Abadir
2006	—	`ed.`	Seventh International Workshop on Microprocessor Test and Verification (MTV 2006), Common Challenges and Solutions, 4-5 December 2006, Austin, Texas, USA MTV Magdy S. Abadir, Li-C. Wang, Jayanta Bhadra
2005	J	`jnl`	A methodology for validation of microprocessors using symbolic simulation. Int. J. Embed. Syst. Prabhat Mishra, Nikil D. Dutt, Narayanan Krishnamurthy, Magdy S. Abadir
2005	—	`conf`	Automatic Generation of High Performance Embedded Memory Models for PowerPC Microprocessors. MTV Jayanta Bhadra, Magdy S. Abadir, David Burgess, Ekaterina Trofimova
2005	A*	`conf`	Choosing flows and methodologies for SoC design. DAC Dennis Wassung, Yervant Zorian, Magdy S. Abadir, Mark Bapst, Colin Harris
2005	—	`conf`	Diagnosing multiple transition faults in the absence of timing information. ACM Great Lakes Symposium on VLSI Jiang Brandon Liu, Magdy S. Abadir, Andreas G. Veneris, Sean Safarpour
2005	—	`conf`	Establishing latch correspondence for embedded circuits of PowerPC microprocessors. HLDVT Himyanshu Anand, Jayanta Bhadra, Alper Sen, Magdy S. Abadir, Kenneth G. Davis
2005	J	`jnl`	Functional Fault Equivalence and Diagnostic Test Generation in Combinational Logic Circuits Using Conventional ATPG. J. Electron. Test. Andreas G. Veneris, Robert Chang, Magdy S. Abadir, Sep Seyedi
2005	A	`conf`	Hazard-aware statistical timing simulation and its applications in screening frequency-dependent defects. ITC Benjamin N. Lee, Hui Li, Li-C. Wang, Magdy S. Abadir
2005	—	`conf`	Post-Verification Debugging of Hierarchical Designs. MTV Moayad Fahim Ali, Sean Safarpour, Andreas G. Veneris, Magdy S. Abadir, Rolf Drechsler
2005	A	`conf`	Post-verification debugging of hierarchical designs. ICCAD Moayad Fahim Ali, Sean Safarpour, Andreas G. Veneris, Magdy S. Abadir, Rolf Drechsler
2005	Misc	`conf`	Recent Advances in Verification, Equivalence Checking and SAT-Solvers. VLSI Design Dhiraj K. Pradhan, Magdy S. Abadir, Mauricio Varea
2005	Misc	`conf`	Reducing Pattern Delay Variations for Screening Frequency Dependent Defects. VTS Benjamin N. Lee, Li-C. Wang, Magdy S. Abadir
2005	—	`conf`	Retiming Verification Using Sequential Equivalence Checking. MTV Brian Kahne, Magdy S. Abadir
2005	—	`ed.`	Sixth International Workshop on Microprocessor Test and Verification (MTV 2005), Common Challenges and Solutions, 3-4 November 2005, Austin, Texas, USA MTV Magdy S. Abadir, Li-C. Wang
2004	J	`jnl`	A Top-Down Methodology for Microprocessor Validation. IEEE Des. Test Comput. Prabhat Mishra, Nikil D. Dutt, Narayanan Krishnamurthy, Magdy S. Abadir
2004	Misc	`conf`	Analytical models for leakage power estimation of memory array structures. CODES+ISSS Mahesh Mamidipaka, Kamal S. Khouri, Nikil D. Dutt, Magdy S. Abadir
2004	—	`conf`	Debugging Sequential Circuits Using Boolean Satisfiability. MTV Moayad Fahim Ali, Andreas G. Veneris, Sean Safarpour, Magdy S. Abadir, Rolf Drechsler, Alexander Smith
2004	A	`conf`	Debugging sequential circuits using Boolean satisfiability. ICCAD Moayad Fahim Ali, Andreas G. Veneris, Alexander Smith, Sean Safarpour, Rolf Drechsler, Magdy S. Abadir
2004	J	`jnl`	Enhanced Equivalence Checking: Toward a Solidarity of Functional Verification and Manufacturing Test Generation. IEEE Des. Test Comput. Jayanta Bhadra, Narayanan Krishnamurthy, Magdy S. Abadir
2004	—	`conf`	Fault equivalence and diagnostic test generation using ATPG. ISCAS (5) Andreas G. Veneris, Robert Chang, Magdy S. Abadir, Mandana Amiri
2004	J	`jnl`	Guest Editors' Introduction: The Verification and Test of Complex Digital ICs. IEEE Des. Test Comput. Magdy S. Abadir, Li-C. Wang
2004	J	`jnl`	IDAP: a tool for high-level power estimation of custom array structures. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Mahesh Mamidipaka, Kamal S. Khouri, Nikil D. Dutt, Magdy S. Abadir
2004	—	`conf`	Identification of Gates for Covering all Critical Paths. MTV M. Moiz Khan, Spyros Tragoudas, Magdy S. Abadir, Jiang Brandon Liu
2004	A	`conf`	On Correlating Structural Tests with Functional Tests for Speed Binning of High Performance Design. ITC Jing Zeng, Magdy S. Abadir, A. Kolhatkar, G. Vandling, Li-C. Wang, Jacob A. Abraham
2004	—	`conf`	On Correlating Structural Tests with Functional Tests for Speed Binning of High Performance Design. MTV Jing Zeng, Magdy S. Abadir, G. Vandling, Li-C. Wang, S. Karako, Jacob A. Abraham
2004	A*	`conf`	On path-based learning and its applications in delay test and diagnosis. DAC Li-C. Wang, T. M. Mak, Kwang-Ting Cheng, Magdy S. Abadir
2004	Misc	`conf`	Towards The Complete Elimination of Gate/Switch Level Simulations. VLSI Design Narayanan Krishnamurthy, Jayanta Bhadra, Magdy S. Abadir, Jacob A. Abraham
2003	—	`conf`	A Methodology for Validating Manufacturing Test Vector Suites for Custom Designed Scan-Based Circuits. MTV Jayanta Bhadra, Narayanan Krishnamurthy, Magdy S. Abadir
2003	—	`conf`	An automated method for test model generation from switch level circuits. ASP-DAC Tim McDougall, Atanas N. Parashkevov, Simon Jolly, Juhong Zhu, Jing Zeng, Carol Pyron, Magdy S. Abadir
2003	—	`conf`	Automated Test Model Generation from Switch Level Custom Circuits. Asian Test Symposium Magdy S. Abadir, Jing Zeng, Carol Pyron, Juhong Zhu
2003	A	`conf`	Delay Defect Diagnosis Based Upon Statistical Timing Models - The First Step. DATE Angela Krstic, Li-C. Wang, Kwang-Ting Cheng, Jing-Jia Liou, Magdy S. Abadir
2003	J	`jnl`	Enhanced Symbolic Simulation for Functional Verification of Embedded Array Systems. Des. Autom. Embed. Syst. Li-C. Wang, Tao Feng, Kwang-Ting (Tim) Cheng, Magdy S. Abadir, Manish Pandey
2003	—	`conf`	Enhanced symbolic simulation for efficient verification of embedded array systems. ASP-DAC Tao Feng, Li-C. Wang, Kwang-Ting Cheng, Manish Pandey, Magdy S. Abadir
2003	J	`jnl`	Formal Verification Successes at Motorola. Formal Methods Syst. Des. Magdy S. Abadir, Ken Albin, John Havlicek, Narayanan Krishnamurthy, Andrew K. Martin
2003	A	`conf`	IDAP: A Tool for High Level Power Estimation of Custom Array Structures. ICCAD Mahesh Mamidipaka, Kamal S. Khouri, Nikil D. Dutt, Magdy S. Abadir
2003	—	`conf`	Logic verification based on diagnosis techniques. ASP-DAC Andreas G. Veneris, Alexander Smith, Magdy S. Abadir
2003	Misc	`conf`	Transition Test Generation using Replicate-and-Reduce Transform for Scan-based Designs. VTS Magdy S. Abadir, Juhong Zhu
2003	A	`conf`	Using Logic Models To Predict The Detection Behavior Of Statistical Timing Defects. ITC Li-C. Wang, Angela Krstic, Leonard Lee, Kwang-Ting Cheng, M. Ray Mercer, Thomas W. Williams, Magdy S. Abadir
2002	A	`conf`	Combining ATPG and Symbolic Simulation for Efficient Validation of Embedded Array Systems. ITC Ganapathy Parthasarathy, Madhu K. Iyer, Tao Feng, Li-C. Wang, Kwang-Ting Cheng, Magdy S. Abadir
2002	A	`conf`	Design Rewiring Using ATPG. ITC Andreas G. Veneris, Magdy S. Abadir, Mandana Amiri
2002	J	`jnl`	Design rewiring using ATPG. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Andreas G. Veneris, Magdy S. Abadir
2002	—	`conf`	Efficient and Exact Diagnosis of Multiple Stuck-At Faults. LATW Jiang Brandon Liu, Andreas G. Veneris, Magdy S. Abadir
2002	A*	`conf`	False timing path identification using ATPG techniques and delay-based information. DAC Jing Zeng, Magdy S. Abadir, Jacob A. Abraham
2002	A	`conf`	Incremental Diagnosis and Correction of Multiple Faults and Errors. DATE Andreas G. Veneris, Jiang Brandon Liu, Mandana Amiri, Magdy S. Abadir
2002	Misc	`conf`	Is State Mapping Essential for Equivalence Checking Custom Memories in Scan-Based Designs? VTS Narayanan Krishnamurthy, Jayanta Bhadra, Magdy S. Abadir, Jacob A. Abraham
2002	A	`conf`	Minimal Test for Coupling Faults in Word-Oriented Memories. DATE Ad J. van de Goor, Magdy S. Abadir, Alan Carlin
2002	A	`conf`	On Testing High-Performance Custom Circuits without Explicit Testing of the Internal Faults. ITC Li-C. Wang, Magdy S. Abadir, Juhong Zhu
2002	—	`conf`	Validation and Verification of Complex Digital Systems: A Practical Perspective. LATW Li-C. Wang, Magdy S. Abadir
2001	—	`conf`	A language formalism for verification of PowerPC HLDVT Jayanta Bhadra, Andrew K. Martin, Jacob A. Abraham, Magdy S. Abadir
2001	—	`conf`	ATPG Driven Logic Synthesis for Delay and Power Minimization. LATW Ivor Ting, Andreas G. Veneris, Magdy S. Abadir
2001	Misc	`conf`	ATPG for Design Errors-Is It Possible? VTS Magdy S. Abadir, Scott Davidson, Vijay Nagasamy, Dhiraj K. Pradhan, Prab Varma
2001	Misc	`conf`	Analysis of Testing Methodologies for Custom Designs in PowerPCTM Microprocessor. VTS Magdy S. Abadir, Juhong Zhu, Li-C. Wang
2001	—	`conf`	Automatic Bias Generation Using Pipeline Instruction State Coverage for Biased Random Instruction Generation. IOLTW Mrinal Bose, Elizabeth M. Rudnick, Magdy S. Abadir
2001	J	`jnl`	Design and Development Paradigm for Industrial Formal Verification CAD Tools. IEEE Des. Test Comput. Narayanan Krishnamurthy, Magdy S. Abadir, Andrew K. Martin, Jacob A. Abraham
2001	—	`conf`	Design rewiring based on diagnosis techniques. ASP-DAC Andreas G. Veneris, Magdy S. Abadir, Ivor Ting
2001	A	`conf`	Full chip false timing path identification: applications to the PowerPCTM microprocessors. DATE Jing Zeng, Magdy S. Abadir, Jayanta Bhadra, Jacob A. Abraham
2001	—	`conf`	Using Abstract Specifications to Verify PowerPC CHARME Jayanta Bhadra, Andrew K. Martin, Jacob A. Abraham, Magdy S. Abadir
2001	—	`conf`	Verification and Validation of Complex Digital Systems: An Industrial Perspective. ISQED Magdy S. Abadir, Li-C. Wang
2001	J	`jnl`	Very Low Cost Testers: Opportunities and Challenges. IEEE Des. Test Comput. Jay Bedsole, Rajesh Raina, Al Crouch, Magdy S. Abadir
2000	—	`conf`	A Quick and Inexpensive Method to Identify False Critical Paths Using ATPG Techniques: an Experiment with a PowerPC Microprocessor. LATW Jayanta Batra, Magdy S. Abadir, Jacob A. Abraham
2000	—	`conf`	A quick and inexpensive method to identify false critical paths using ATPG techniques: an experiment with a PowerPC CICC Jayanta Bhadra, Magdy S. Abadir, Jacob A. Abraham
2000	—	`conf`	Design Optimization Based on Diagnosis Techniques. LATW Andreas G. Veneris, Magdy S. Abadir, Ibrahim N. Haji
2000	J	`jnl`	Guest Editorial. J. Electron. Test. Magdy S. Abadir
2000	J	`jnl`	Guest Editors' Introduction: Microprocessor Test and Verification. IEEE Des. Test Comput. Magdy S. Abadir, Sumit DasGupta
2000	J	`jnl`	On Efficiently Producing Quality Tests for Custom Circuits in PowerPC J. Electron. Test. Li-C. Wang, Magdy S. Abadir
2000	J	`jnl`	Oscillation Ring Delay Test for High Performance Microprocessors. J. Electron. Test. Wen Ching Wu, Chung-Len Lee, Ming Shae Wu, Jwu E. Chen, Magdy S. Abadir
2000	J	`jnl`	Validating PowerPC Microprocessor Custom Memories. IEEE Des. Test Comput. Narayanan Krishnamurthy, Andrew K. Martin, Magdy S. Abadir, Jacob A. Abraham
2000	Misc	`conf`	Validation of PowerPC(tm) Custom Memories using Symbolic Simulation. VTS Narayanan Krishnamurthy, Andrew K. Martin, Magdy S. Abadir, Jacob A. Abraham
1999	A	`conf`	Design-for-test methodology for Motorola PowerPC microprocessors. ITC Magdy S. Abadir, Rajesh Raina
1999	J	`jnl`	Experience in Validation of PowerPCTM Microprocessor Embedded Arrays. J. Electron. Test. Li-C. Wang, Magdy S. Abadir
1999	A	`conf`	Tradeoff analysis for producing high quality tests for custom circuits in PowerPC microprocessors. ITC Li-C. Wang, Magdy S. Abadir
1998	A*	`conf`	Automatic Generation of Assertions for Formal Verification of PowerPC Microprocessor Arrays Using Symbolic Trajectory Evaluation. DAC Li-C. Wang, Magdy S. Abadir, Nari Krishnamurthy
1998	A	`conf`	Measuring the Effectiveness of Various Design Validation Approaches For PowerPC(TM) Microprocessor Arrays. DATE Li-C. Wang, Magdy S. Abadir, Jing Zeng
1998	Misc	`conf`	On Logic and Transistor Level Design Error Detection of Various Validation Approaches for PowerPC(tm) Microprocessor Arrays. VTS Li-C. Wang, Magdy S. Abadir, Jing Zeng
1998	J	`jnl`	On measuring the effectiveness of various design validation approaches for PowerPC microprocessor embedded arrays. ACM Trans. Design Autom. Electr. Syst. Li-C. Wang, Magdy S. Abadir, Jing Zeng
1998	—	`conf`	Practical Considerations in Formal Equivalence Checking of PowerPC(tm) Microprocessors. Great Lakes Symposium on VLSI Arun Chandra, Li-C. Wang, Magdy S. Abadir
1998	J	`jnl`	Test Generation Based on High-Level Assertion Specification for PowerPCTM Microprocessor Embedded Arrays. J. Electron. Test. Li-C. Wang, Magdy S. Abadir
1997	A	`conf`	A New Validation Methodology Combining Test and Formal Verification for PowerPC ITC Li-C. Wang, Magdy S. Abadir
1997	J	`jnl`	Cost-Driven Ranking of Memory Elements for Partial Intrusion. IEEE Des. Test Comput. Magdy S. Abadir, Rohit Kapur
1997	J	`jnl`	Design and Test Economics-An Extra Dimension. IEEE Des. Test Comput. Tony Ambler, Magdy S. Abadir
1997	J	`jnl`	Economic Analysis of Test Process Flows for Multichip Modules Using Known Good Die. J. Electron. Test. Cynthia F. Murphy, Magdy S. Abadir, Peter Sandborn
1997	A*	`conf`	Formal Verification of Content Addressable Memories Using Symbolic Trajectory Evaluation. DAC Manish Pandey, Richard Raimi, Randal E. Bryant, Magdy S. Abadir
1997	J	`jnl`	Indexed BDDs: Algorithmic Advances in Techniques to Represent and Verify Boolean Functions. IEEE Trans. Computers Jawahar Jain, James R. Bitner, Magdy S. Abadir, Jacob A. Abraham, Donald S. Fussell
1997	Misc	`conf`	Microprocessor Test and Validation: Any New Avenues? VTS Magdy S. Abadir, Jacob A. Abraham, Hong Hao, C. Hunter, Wayne M. Needham, Ron G. Walther
1996	A	`conf`	PowerPC ITC Neeta Ganguly, Magdy S. Abadir, Manish Pandey
1994	J	`jnl`	Analyzing Multichip Module Testing Strategies. IEEE Des. Test Comput. Magdy S. Abadir, Ashish R. Parikh, Linda Bal, Peter Sandborn, Ken Drake
1994	—	`conf`	Efficient Algorithmic Circuit Verification Using Indexed BDDs. FTCS James R. Bitner, Jawahar Jain, Magdy S. Abadir, Jacob A. Abraham, Donald S. Fussell
1994	J	`jnl`	High Level Test Economics Advisor (Hi-TEA). J. Electron. Test. Magdy S. Abadir, Ashish Parikh, Linda Bal, Peter Sandborn, Cynthia F. Murphy
1994	J	`jnl`	Introduction. J. Electron. Test. Magdy S. Abadir, Tony Ambler
1994	J	`jnl`	Multichip systems trade-off analysis tool. J. Electron. Test. Peter Sandborn, Rajarshi Ghosh, Ken Drake, Magdy S. Abadir, Linda Bal, Ashish Parikh
1993	C	`conf`	AMBIANT: Automatic Generation of Behavioral Modifications for Testability. ICCD Praveen Vishakantaiah, Thomas Thomas, Jacob A. Abraham, Magdy S. Abadir
1992	A*	`conf`	Automatic Test Knowledge Extraction from VHDL (ATKET). DAC Praveen Vishakantaiah, Jacob A. Abraham, Magdy S. Abadir
1991	A	`conf`	Partitioning Hierarchical Designs for Testability. ITC Magdy S. Abadir, Joe Newman, Desmond D'Souza, Steve Spencer
1990	—	`conf`	An improved layout verification algorithm (LAVA). EURO-DAC Magdy S. Abadir, Jack Ferguson
1989	A	`conf`	TIGER: testability insertion guidance expert system. ICCAD Magdy S. Abadir
1988	J	`jnl`	Logic design verification via test generation. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Magdy S. Abadir, Jack Ferguson, Tom E. Kirkland
1986	J	`jnl`	Functional Test Generation for Digital Circuits Described Using Binary Decision Diagrams. IEEE Trans. Computers Magdy S. Abadir, Hassan K. Reghbati
1986	A	`conf`	Scan Path with Look Ahead Shifting (SPLASH). ITC Magdy S. Abadir, Melvin A. Breuer
1986	J	`jnl`	Test Schedules for VLSI Circuits Having Built-In Test Hardware. IEEE Trans. Computers Magdy S. Abadir, Melvin A. Breuer
1985	J	`jnl`	A Knowledge-Based System for Designing Testable VLSI Chips. IEEE Des. Test Magdy S. Abadir, Melvin A. Breuer
1985	A	`conf`	Functional Test Generation for LSI Circuits Described by Binary Decision Diagrams. ITC Magdy S. Abadir, Hassan K. Reghbati
1984	A*	`conf`	Test generation for LSI: A case study. DAC Magdy S. Abadir, Hassan K. Reghbati
1983	J	`jnl`	Functional Testing of Semiconductor Random Access Memories. ACM Comput. Surv. Magdy S. Abadir, Hassan K. Reghbati
1983	J	`jnl`	LSI Testing Techniques. IEEE Micro Magdy S. Abadir, Hassan K. Reghbati