Madhura Purnaprajna

31 papers A 2B 2Misc 9Journal 10Unranked 7

Year	Rank	Type	Title / Venue / Authors
2025	—	`conf`	MATANALYZE - A Custom Accelerator Generator for Sparse × Dense and Dense × Sparse Matrix Multiplication. HiPCW Mohammed Sahel, Disha Kiran D, M. R. Ashuthosh, Madhura Purnaprajna
2025	Misc	`conf`	Optimization of Sub-Threshold Standard Cells for Energy Efficient Designs. VLSID Vardhan Suroshi, Karthik B. K, Vikram Kannur, Vinay Reddy, Madhura Purnaprajna
2025	—	`conf`	PARISCV: A RISC-V Profiler for Application-Specific Hardware Optimization. HiPCW Spoorthi S, M. R. Ashuthosh, Bharadhwaj K, Vinay Reddy, Madhura Purnaprajna
2023	J	`jnl`	Enabling High-Level Design Strategies for High-Throughput and Low-Power NB-LDPC Decoders. IEEE Des. Test Srinivasan Subramaniyan, Oscar Ferraz, M. R. Ashuthosh, Santosh Krishna, Guohui Wang, Joseph R. Cavallaro, Vítor Silva, Gabriel Falcão, Madhura Purnaprajna
2022	J	`jnl`	A Survey on High-Throughput Non-Binary LDPC Decoders: ASIC, FPGA, and GPU Architectures. IEEE Commun. Surv. Tutorials Oscar Ferraz, Srinivasan Subramaniyan, Ramesh Chinthala, João Andrade, Joseph R. Cavallaro, Soumitra Kumar Nandy, Vítor Silva, Xinmiao Zhang, Madhura Purnaprajna, Gabriel Falcão
2022	Misc	`conf`	MAPPARAT: A Resource Constrained FPGA-Based Accelerator for Sparse-Dense Matrix Multiplication. VLSID M. R. Ashuthosh, Santosh Krishna, Vishvas Sudarshan, Srinivasan Subramaniyan, Madhura Purnaprajna
2021	Misc	`conf`	Demystifying Compression Techniques in CNNs: CPU, GPU and FPGA cross-platform analysis. VLSID Remya Ramakrishnan, Aditya K. V. Dev, Darshik A. S, Renuka Chinchwadkar, Madhura Purnaprajna
2021	J	`jnl`	TileNET: Hardware accelerator for ternary Convolutional Neural Networks. Microprocess. Microsystems Sagar Eetha, Sruthi P. K., Vibha Panty, Sahu Sai Vikram, Mihir Mody, Madhura Purnaprajna
2020	Misc	`conf`	Gbit/s Non-Binary LDPC Decoders: High-Throughput using High-Level Specifications. FCCM Oscar Ferraz, Srinivasan Subramaniyan, Guohui Wang, Joseph R. Cavallaro, Gabriel Falcão, Madhura Purnaprajna
2020	—	`conf`	Pushing the Limits of Energy Efficiency for Non-Binary LDPC Decoders on GPUs and FPGAs. SiPS Srinivasan Subramaniyan, Oscar Ferraz, M. R. Ashuthosh, Santosh Krishna, Guohui Wang, Joseph R. Cavallaro, Vítor Silva, Gabriel Falcão, Madhura Purnaprajna
2020	J	`jnl`	Recurrent Neural Networks: An Embedded Computing Perspective. IEEE Access Nesma M. Rezk, Madhura Purnaprajna, Tomas Nordström, Zain Ul-Abdin
2019	J	`jnl`	Recurrent Neural Networks: An Embedded Computing Perspective. CoRR Nesma M. Rezk, Madhura Purnaprajna, Tomas Nordström, Zain Ul-Abdin
2019	Misc	`conf`	k-Core: Hardware Accelerator for k-Mer Generation and Counting used in Computational Genomics. VLSID Simmi M. Bose, Varsha S. Lalapura, S. Saravanan, Madhura Purnaprajna
2018	Misc	`conf`	Performance modeling for data distribution in heterogeneous computing systems: work in progress. CASES Vanishree K, Madhura Purnaprajna
2018	—	`conf`	Streaming Tiles: Flexible Implementation of Convolution Neural Networks Inference on Manycore Architectures. IPDPS Workshops Nesma M. Rezk, Madhura Purnaprajna, Zain Ul-Abdin
2018	Misc	`conf`	TileNET: Scalable Architecture for High-Throughput Ternary Convolution Neural Networks Using FPGAs. VLSID Sahu Sai Vikram, Vibha Panty, Mihir Mody, Madhura Purnaprajna
2015	B	`conf`	Enabling seamless execution on hybrid CPU/FPGA systems: Challenges & directions. FPL Meena Belwal, Madhura Purnaprajna, T. S. B. Sudarshan
2015	J	`jnl`	Enhancing Design Space Exploration by Extending CPU/GPU Specifications onto FPGAs. ACM Trans. Embed. Comput. Syst. Muhsen Owaida, Gabriel Falcão, João Andrade, Christos D. Antonopoulos, Nikolaos Bellas, Madhura Purnaprajna, David Novo, Georgios Karakonstantis, Andreas Burg, Paolo Ienne
2013	Misc	`conf`	A Case for Heterogeneous Technology-Mapping: Soft Versus Hard Multiplexers. FCCM Madhura Purnaprajna, Paolo Ienne
2013	A	`conf`	Shadow AICs: reaping the benefits of and-inverter cones with minimal architectural impact (abstract only). FPGA Hadi Parandeh-Afshar, Grace Zgheib, David Novo, Madhura Purnaprajna, Paolo Ienne
2013	B	`conf`	Shadow And-Inverter Cones. FPL Hadi Parandeh-Afshar, Grace Zgheib, David Novo, Madhura Purnaprajna, Paolo Ienne
2012	J	`jnl`	Making wide-issue VLIW processors viable on FPGAs. ACM Trans. Archit. Code Optim. Madhura Purnaprajna, Paolo Ienne
2012	Misc	`conf`	Shortening Design Time through Multiplatform Simulations with a Portable OpenCL Golden-model: The LDPC Decoder Case. FCCM Gabriel Falcão, Muhsen Owaida, David Novo, Madhura Purnaprajna, Nikolaos Bellas, Christos D. Antonopoulos, Georgios Karakonstantis, Andreas Burg, Paolo Ienne
2010	—	`—`	Run-time reconfigurable multiprocessors. Madhura Purnaprajna
2010	J	`jnl`	Runtime Reconfiguration of Multiprocessors Based on Compile-Time Analysis. ACM Trans. Reconfigurable Technol. Syst. Madhura Purnaprajna, Mario Porrmann, Ulrich Rückert, Michael Hussmann, Michael Thies, Uwe Kastens
2009	J	`jnl`	Run-time reconfigurability in embedded multiprocessors. SIGARCH Comput. Archit. News Madhura Purnaprajna, Mario Porrmann, Ulrich Rückert
2009	—	`conf`	Self-optimization of MPSoCs Targeting Resource Efficiency and Fault Tolerance. AHS Mario Porrmann, Madhura Purnaprajna, Christoph Puttmann
2009	—	`conf`	Using Run-time Reconfiguration for Energy Savings in Parallel Data Processing. ERSA Madhura Purnaprajna, Christopher Pohl, Mario Porrmann, Ulrich Rückert
2008	A	`conf`	Power Aware Reconfigurable Multiprocessor for Elliptic Curve Cryptography. DATE Madhura Purnaprajna, Christoph Puttmann, Mario Porrmann
2007	J	`jnl`	Genetic algorithms for hardware-software partitioning and optimal resource allocation. J. Syst. Archit. Madhura Purnaprajna, Marek Z. Reformat, Witold Pedrycz
2004	—	`conf`	Genetic Algorithms in Hardware-Software Partitioning. ERSA Madhura Purnaprajna, Marek Z. Reformat, Witold Pedrycz