Madhu Mutyam - RankMe

80 papers A 8B 6C 7Misc 5Journal 33Unranked 21

Year	Rank	Type	Title / Venue / Authors
2025	J	`jnl`	Selective Subarray Isolation for Mitigating RowHammer Attack. ACM Trans. Embed. Comput. Syst. Praseetha M, Madhu Mutyam, Venkata Kalyan Tavva
2024	B	`conf`	Cache Line Pinning for Mitigating Row Hammer Attack. ICPP Praseetha M, Madhu Mutyam, Venkata Kalyan Tavva
2024	B	`conf`	Selective Memory Compression for GPU Memory Oversubscription Management. ICPP Abdun Nihaal, Madhu Mutyam
2023	J	`jnl`	Formal Modeling and Verification of Security Properties of a Ransomware-Resistant SSD. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Shivani Tripathy, Debiprasanna Sahoo, Manoranjan Satpathy, Madhu Mutyam
2020	J	`jnl`	A Scalable and Energy-Efficient Concurrent Binary Search Tree With Fatnodes. IEEE Trans. Sustain. Comput. Praveen Alapati, Venkata Kalyan Tavva, Madhu Mutyam
2020	J	`jnl`	Concurrent Treaps and Impact of Locking Objects. New Gener. Comput. Praveen Alapati, Madhu Mutyam, Swamy Saranam
2020	A	`conf`	Fuzzy fairness controller for NVMe SSDs. ICS Shivani Tripathy, Debiprasanna Sahoo, Manoranjan Satpathy, Madhu Mutyam
2020	J	`jnl`	Optimization of Intercache Traffic Entanglement in Tagless Caches With Tiling Opportunities. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. S. R. Swamy Saranam Chongala, Sumitha George, Hariram Thirucherai Govindarajan, Jagadish Kotra, Madhu Mutyam, John Sampson, Mahmut T. Kandemir, Vijaykrishnan Narayanan
2020	C	`conf`	Router Buffer Caching for Managing Shared Cache Blocks in Tiled Multi-Core Processors. ICCD Joe Augustine, Kanakagiri Raghavendra, John Jose, Madhu Mutyam
2019	—	`conf`	Endurance enhancement of write-optimized STT-RAM caches. MEMSYS Puneet Saraf, Madhu Mutyam
2019	J	`jnl`	Formal Modeling and Verification of a Victim DRAM Cache. ACM Trans. Design Autom. Electr. Syst. Debiprasanna Sahoo, Swaraj Sha, Manoranjan Satpathy, Madhu Mutyam, S. Ramesh, Partha S. Roop
2019	B	`conf`	POSTER: Variable Sized Cache-Block Compaction. PACT Sayantan Ray, Madhu Mutyam
2019	C	`conf`	Post-Model Validation of Victim DRAM Caches. ICCD Debiprasanna Sahoo, Shivani Tripathy, Manoranjan Satpathy, Madhu Mutyam
2018	—	`conf`	CAMO: A novel cache management organization for GPGPUs. ASP-DAC Debiprasanna Sahoo, Swaraj Sha, Manoranjan Satpathy, Madhu Mutyam, Laxmi Narayan Bhuyan
2018	J	`jnl`	Formal Modeling and Verification of Controllers for a Family of DRAM Caches. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Debiprasanna Sahoo, Swaraj Sha, Manoranjan Satpathy, Madhu Mutyam, S. Ramesh, Partha S. Roop
2018	J	`jnl`	ReDRAM: A Reconfigurable DRAM Cache for GPGPUs. IEEE Comput. Archit. Lett. Debiprasanna Sahoo, Swaraj Sha, Manoranjan Satpathy, Madhu Mutyam
2018	—	`conf`	TDC: Tagless DRAM Cache. ISVLSI S. R. Swamy Saranam, Madhu Mutyam
2017	Misc	`conf`	An Experimental Study on Dynamic Bank Partitioning of DRAM in Chip Multiprocessors. VLSID Debiprasanna Sahoo, Manoranjan Satpathy, Madhu Mutyam
2017	C	`conf`	Concurrent Treaps. ICA3PP Praveen Alapati, Swamy Saranam, Madhu Mutyam
2017	—	`conf`	FatCBST: Concurrent Binary Search Tree with Fatnodes. HPCC/SmartCity/DSS Praveen Alapati, Venkata Kalyan Tavva, Madhu Mutyam
2017	J	`jnl`	MBZip: Multiblock Data Compression. ACM Trans. Archit. Code Optim. Kanakagiri Raghavendra, Biswabandan Panda, Madhu Mutyam
2017	C	`conf`	RCTP: Region Correlated Temporal Prefetcher. ICCD Dennis Antony Varkey, Biswabandan Panda, Madhu Mutyam
2016	—	`conf`	CASCADE: Congestion Aware Switchable Cycle Adaptive Deflection Router. ARCS Gnaneswara Rao Jonna, Vamana Murthi Thuniki, Madhu Mutyam
2016	J	`jnl`	PBC: Prefetched Blocks Compaction. IEEE Trans. Computers Kanakagiri Raghavendra, Biswabandan Panda, Madhu Mutyam
2015	J	`jnl`	SkipCache: application aware cache management for chip multi-processors. IET Comput. Digit. Tech. Tripti S. Warrier, Kanakagiri Raghavendra, Madhu Mutyam
2014	B	`conf`	Data remapping for an energy efficient burst chop in DRAM memory systems. PACT Sudharsan Jagathrakshakan, Venkata Kalyan Tavva, Madhu Mutyam
2014	J	`jnl`	EFGR: An Enhanced Fine Granularity Refresh Feature for High-Performance DDR4 DRAM Devices. ACM Trans. Archit. Code Optim. Venkata Kalyan Tavva, Ravi Kasha, Madhu Mutyam
2014	J	`jnl`	Implementation and Analysis of History-Based Output Channel Selection Strategies for Adaptive Routers in Mesh NoCs. ACM Trans. Design Autom. Electr. Syst. John Jose, Madhu Mutyam
2014	A	`conf`	Minimally buffered single-cycle deflection router. DATE Gnaneswara Rao Jonna, John Jose, Rachana Radhakrishnan, Madhu Mutyam
2014	—	`conf`	SAMO: store aware memory optimizations. Conf. Computing Frontiers Kanakagiri Raghavendra, Tripti S. Warrier, Madhu Mutyam
2014	C	`conf`	SFFMap: Set-First Fill mapping for an energy efficient pipelined data cache. ICCD Pritam Majumder, T. Venkata Kalyan, Madhu Mutyam
2014	—	`conf`	Scattered refresh: An alternative refresh mechanism to reduce refresh cycle time. ASP-DAC T. Venkata Kalyan, Ravi Kasha, Madhu Mutyam
2014	—	`conf`	Using packet information for efficient communication in NoCs. NOCS Prasanna Venkatesh Rengasamy, Madhu Mutyam
2013	—	`conf`	An Application-Aware Cache Replacement Policy for Last-Level Caches. ARCS Tripti S. Warrier, B. Anupama, Madhu Mutyam
2013	A	`conf`	DeBAR: deflection based adaptive router with minimal buffering. DATE John Jose, Bhawna Nayak, Damarla Kranthi Kumar, Madhu Mutyam
2013	J	`jnl`	Prevention slot flow-control mechanism for low latency torus network-on-chip. IET Comput. Digit. Tech. Arpit Joshi, Prasanna Venkatesh Rengasamy, Madhu Mutyam
2013	C	`conf`	SLIDER: Smart Late Injection DEflection Router for mesh NoCs. ICCD Bhawna Nayak, John Jose, Madhu Mutyam
2012	J	`jnl`	Fibonacci Codes for Crosstalk Avoidance. IEEE Trans. Very Large Scale Integr. Syst. Madhu Mutyam
2012	B	`conf`	SkipCache: miss-rate aware cache management. PACT Kanakagiri Raghavendra, Tripti S. Warrier, Madhu Mutyam
2012	A	`conf`	TRACKER: A low overhead adaptive NoC router with load balancing selection strategy. ICCAD John Jose, K. V. Mahathi, J. Shiva Shankar, Madhu Mutyam
2012	Misc	`conf`	Way Sharing Set Associative Cache Architecture. VLSI Design C. J. Janraj, T. Venkata Kalyan, Tripti S. Warrier, Madhu Mutyam
2011	—	`conf`	BOFAR: buffer occupancy factor based adaptive router for mesh NoCs. NoCArc@MICRO John Jose, J. Shiva Shankar, K. V. Mahathi, Damarla Kranthi Kumar, Madhu Mutyam
2011	—	`conf`	Prevention flow-control for low latency torus networks-on-chip. NOCS Arpit Joshi, Madhu Mutyam
2011	J	`jnl`	Timing variation-aware scheduling and resource binding in high-level synthesis. ACM Trans. Design Autom. Electr. Syst. Kartikey Mittal, Arpit Joshi, Madhu Mutyam
2009	J	`jnl`	Delay-efficient bus encoding techniques. Microprocess. Microsystems Nallamothu Satyanarayana, A. Vinaya Babu, Madhu Mutyam
2009	J	`jnl`	Process-Variation-Aware Adaptive Cache Architecture and Management. IEEE Trans. Computers Madhu Mutyam, Feng Wang, Krishnan Ramakrishnan, Vijaykrishnan Narayanan, Mahmut T. Kandemir, Yuan Xie, Mary Jane Irwin
2009	J	`jnl`	Selective shielding technique to eliminate crosstalk transitions. ACM Trans. Design Autom. Electr. Syst. Madhu Mutyam
2008	—	`conf`	Block remap with turnoff: A variation-tolerant cache design technique. ASP-DAC Mohammed Abid Hussain, Madhu Mutyam
2008	Misc	`conf`	Exploiting Variable Cycle Transmission for Energy-Efficient On-Chip Interconnect Design. VLSI Design T. Venkata Kalyan, Madhu Mutyam, Vijaya Sankara Rao Pasupureddi
2008	—	`conf`	Power management of variation aware chip multiprocessors. ACM Great Lakes Symposium on VLSI Abu Saad Papa, Madhu Mutyam
2008	A	`conf`	Process Variation Aware Issue Queue Design. DATE Kanakagiri Raghavendra, Madhu Mutyam
2008	A	`conf`	Word-interleaved cache: an energy efficient data cache architecture. ISLPED T. Venkata Kalyan, Madhu Mutyam
2007	—	`conf`	Exploiting on-chip data behavior for delay minimization. SLIP Nallamothu Satyanarayana, Madhu Mutyam, A. Vinaya Babu
2007	—	`conf`	Investigating Simple Low Latency Reliable Multiported Register Files. ISVLSI Andrew J. Ricketts, Madhu Mutyam, Narayanan Vijaykrishnan, Mary Jane Irwin
2007	A	`conf`	Selective shielding: a crosstalk-free bus encoding technique. ICCAD Madhu Mutyam
2007	—	`conf`	Variation Analysis of CAM Cells. ISQED Amol Mupid, Madhu Mutyam, Narayanan Vijaykrishnan, Yuan Xie, Mary Jane Irwin
2007	A	`conf`	Working with process variation aware caches. DATE Madhu Mutyam, Narayanan Vijaykrishnan
2006	B	`conf`	Compiler-directed thermal management for VLIW functional units. LCTES Madhu Mutyam, Feihui Li, Narayanan Vijaykrishnan, Mahmut T. Kandemir, Mary Jane Irwin
2006	—	`conf`	Delay and Energy Efficient Data Transmission for On-Chip Buses. ISVLSI Madhu Mutyam, Melvin Eze, Narayanan Vijaykrishnan, Yuan Xie
2006	—	`conf`	Delay and peak power minimization for on-chip buses using temporal redundancy. ACM Great Lakes Symposium on VLSI K. Najeeb, Vishal Gupta, V. Kamakoti, Madhu Mutyam
2006	J	`jnl`	Temporal Redundancy Based Encoding Technique for Peak Power and Delay Reduction of On-Chip Buses. J. Low Power Electron. K. Najeeb, Vishal Gupta, V. Kamakoti, Madhu Mutyam
2005	J	`jnl`	On Characterizing Recursively Enumerable Languages by Insertion Grammars. Fundam. Informaticae Madhu Mutyam, Kamala Krithivasan, A. Siddhartha Reddy
2005	J	`jnl`	Rewriting P systems: improved hierarchies. Theor. Comput. Sci. Madhu Mutyam
2004	Misc	`conf`	A Bus Encoding Technique for Power and Cross-talk Minimization. VLSI Design P. Subrahmanya, R. Manimegalai, V. Kamakoti, Madhu Mutyam
2004	J	`jnl`	Descriptional Complexity of Rewriting P Systems. J. Autom. Lang. Comb. Madhu Mutyam
2004	J	`jnl`	Length Synchronization Context-Free Grammars. J. Autom. Lang. Comb. Madhu Mutyam, Kamala Krithivasan
2004	Misc	`conf`	Preventing Crosstalk Delay using Fibonacci Representation. VLSI Design Madhu Mutyam
2004	J	`jnl`	Rewriting Tissue P Systems. J. Univers. Comput. Sci. Madhu Mutyam, Vaka Jaya Prakash, Kamala Krithivasan
2003	J	`jnl`	Array-rewriting P systems. Nat. Comput. Rodica Ceterchi, Madhu Mutyam, Gheorghe Paun, K. G. Subramanian
2003	J	`jnl`	On a class of P automata. Int. J. Comput. Math. Madhu Mutyam, Kamala Krithivasan
2003	J	`jnl`	Probabilistic Rewriting P Systems. Int. J. Found. Comput. Sci. Madhu Mutyam
2003	J	`jnl`	Some Variants in Communication of Parallel Communicating Pushdown Automata. J. Autom. Lang. Comb. M. Sakthi Balan, Kamala Krithivasan, Madhu Mutyam
2002	J	`jnl`	A Note on Hybrid P Systems. Grammars Madhu Mutyam, Kamala Krithivasan
2002	—	`conf`	A Survey of Some Variants of P Systems. WMC-CdeA Madhu Mutyam, Kamala Krithivasan
2002	—	`conf`	Complexity Issues in Rewriting P Systems. DCFS Madhu Mutyam
2002	J	`jnl`	Contextual P Systems. Fundam. Informaticae Kamala Krithivasan, Madhu Mutyam
2002	J	`jnl`	Generalized normal form for rewriting P systems. Acta Informatica Madhu Mutyam, Kamala Krithivasan
2002	J	`jnl`	Improved Results about Universality of P systems. Bull. EATCS Madhu Mutyam, Kamala Krithivasan
2001	C	`conf`	P Systems with Membrane Creation: Universality and Efficiency. MCU Madhu Mutyam, Kamala Krithivasan
2000	—	`conf`	Universality Results for Some Variants of P Systems. WMP Madhu Mutyam, Kamala Krithivasan