Madhavan Manivannan

37 papers A* 2A 9B 4C 1Journal 17Unranked 3

Year	Rank	Type	Title / Venue / Authors
2024	A	`conf`	SWEEP: Adaptive Task Scheduling for Exploring Energy Performance Trade-offs. IPDPS Jing Chen, Madhavan Manivannan, Bhavishya Goel, Miquel Pericàs
2023	J	`jnl`	Approx-RM: Reducing Energy on Heterogeneous Multicore Processors under Accuracy and Timing Constraints. ACM Trans. Archit. Code Optim. Muhammad Waqar Azhar, Madhavan Manivannan, Per Stenström
2023	B	`conf`	JOSS: Joint Exploration of CPU-Memory DVFS and Task Scheduling for Energy Efficiency. ICPP Jing Chen, Madhavan Manivannan, Bhavishya Goel, Miquel Pericàs
2023	J	`jnl`	JOSS: Joint Exploration of CPU-Memory DVFS and Task Scheduling for Energy Efficiency. CoRR Jing Chen, Madhavan Manivannan, Bhavishya Goel, Miquel Pericàs
2023	—	`conf`	SCALE: Secure and Scalable Cache Partitioning. HOST Nadja Ramhöj Holtryd, Madhavan Manivannan, Per Stenström
2023	A	`conf`	SoK: Analysis of Root Causes and Defense Strategies for Attacks on Microarchitectural Optimizations. EuroS&P Nadja Ramhöj Holtryd, Madhavan Manivannan, Per Stenström
2023	—	`conf`	eProcessor: European, Extendable, Energy-Efficient, Extreme-Scale, Extensible, Processor Ecosystem. CF Lluc Alvarez, Abraham Ruiz, Arnau Bigas-Soldevilla, Pavel Kuroedov, Alberto González, Hamsika Mahale, Noe Bustamante, Albert Aguilera, Francesco Minervini, Javier Salamero, Oscar Palomar, Vassilis Papaefstathiou, Antonis Psathakis, Nikolaos Dimou, Michalis Giaourtas, Iasonas Mastorakis, Georgios Ieronymakis, Georgios-Michail Matzouranis, Vassilis Flouris, Nick Kossifidis, Manolis Marazakis, Bhavishya Goel, Madhavan Manivannan, Ahsen Ejaz, Panagiotis Strikos, Mateo Vázquez, Ioannis Sourdis, Pedro Trancoso, Per Stenström, Jens Hagemeyer, Lennart Tigges, Nils Kucza, Jean-Marc Philippe, Ioannis Papaefstathiou
2022	J	`jnl`	Cooperative Slack Management: Saving Energy of Multicore Processors by Trading Performance Slack Between QoS-Constrained Applications. ACM Trans. Archit. Code Optim. Mehrzad Nejat, Madhavan Manivannan, Miquel Pericàs, Per Stenström
2022	J	`jnl`	ERASE: Energy Efficient Task Mapping and Resource Management for Work Stealing Runtimes. CoRR Jing Chen, Madhavan Manivannan, Mustafa Abduljabbar, Miquel Pericàs
2022	J	`jnl`	ERASE: Energy Efficient Task Mapping and Resource Management for Work Stealing Runtimes. ACM Trans. Archit. Code Optim. Jing Chen, Madhavan Manivannan, Mustafa Abduljabbar, Miquel Pericàs
2022	C	`conf`	STEER: Asymmetry-aware Energy Efficient Task Scheduler for Cluster-based Multicore Architectures. SBAC-PAD Jing Chen, Madhavan Manivannan, Bhavishya Goel, Mustafa Abduljabbar, Miquel Pericàs
2022	J	`jnl`	SoK: Analysis of Root Causes and Defense Strategies for Attacks on Microarchitectural Optimizations. CoRR Nadja Ramhöj Holtryd, Madhavan Manivannan, Per Stenström
2021	B	`conf`	CBP: Coordinated management of cache partitioning, bandwidth partitioning and prefetch throttling. PACT Nadja Ramhöj Holtryd, Madhavan Manivannan, Per Stenström, Miquel Pericàs
2021	J	`jnl`	CBP: Coordinated management of cache partitioning, bandwidth partitioning and prefetch throttling. CoRR Nadja Ramhöj Holtryd, Madhavan Manivannan, Per Stenström, Miquel Pericàs
2020	A	`conf`	Coordinated Management of Processor Configuration and Cache Partitioning to Optimize Energy under QoS Constraints. IPDPS Mehrzad Nejat, Madhavan Manivannan, Miquel Pericàs, Per Stenström
2020	J	`jnl`	Coordinated management of DVFS and cache partitioning under QoS constraints to save energy in multi-core systems. J. Parallel Distributed Comput. Mehrzad Nejat, Madhavan Manivannan, Miquel Pericàs, Per Stenström
2020	A	`conf`	DELTA: Distributed Locality-Aware Cache Partitioning for Tile-based Chip Multiprocessors. IPDPS Nadja Holtryd, Madhavan Manivannan, Per Stenström, Miquel Pericàs
2020	A	`conf`	Enhancing Multithreaded Performance of Asymmetric Multicores with SIMD Offloading. DATE Jeckson Dellagostin Souza, Madhavan Manivannan, Miquel Pericàs, Antonio Carlos Schneider Beck
2020	A*	`conf`	Enhancing Thread-Level Parallelism in Asymmetric Multicores using Transparent Instruction Offloading. DAC Jeckson Dellagostin Souza, Madhavan Manivannan, Miquel Pericàs, Antonio Carlos Schneider Beck
2020	A	`conf`	LEGaTO: Low-Energy, Secure, and Resilient Toolset for Heterogeneous Computing. DATE Behzad Salami, Konstantinos Parasyris, Adrián Cristal, Osman S. Unsal, Xavier Martorell, Paul Carpenter, Raúl de la Cruz, Leonardo Bautista-Gomez, Daniel A. Jiménez, Carlos Álvarez, Seyed Saber Nabavi Larimi, Sergi Madonar, Miquel Pericàs, Pedro Trancoso, Mustafa Abduljabbar, Jing Chen, Pirah Noor Soomro, Madhavan Manivannan, Micha vor dem Berge, Stefan Krupop, Frank Klawonn, Al Mekhlafi, Sigrun May, Tobias Becker, Georgi Gaydadjiev, Hans Salomonsson, Devdatt P. Dubhashi, Oron Port, Yoav Etsion, Do Le Quoc, Christof Fetzer, Martin Kaiser, Nils Kucza, Jens Hagemeyer, René Griessl, Lennart Tigges, Kevin Mika, A. Hüffmeier, Marcelo Pasin, Valerio Schiavoni, Isabelly Rocha, Christian Göttel, Pascal Felber
2020	—	`conf`	Scheduling Task-parallel Applications in Dynamically Asymmetric Environments. ICPP Workshops Jing Chen, Pirah Noor Soomro, Mustafa Abduljabbar, Madhavan Manivannan, Miquel Pericàs
2020	J	`jnl`	Scheduling Task-parallel Applications in Dynamically Asymmetric Environments. CoRR Jing Chen, Pirah Noor Soomro, Mustafa Abduljabbar, Madhavan Manivannan, Miquel Pericàs
2019	J	`jnl`	Coordinated Management of DVFS and Cache Partitioning under QoS Constraints to Save Energy in Multi-Core Systems. CoRR Mehrzad Nejat, Madhavan Manivannan, Miquel Pericàs, Per Stenström
2019	J	`jnl`	Coordinated Management of Processor Configuration and Cache Partitioning to Optimize Energy under QoS Constraints. CoRR Mehrzad Nejat, Madhavan Manivannan, Miquel Pericàs, Per Stenström
2019	J	`jnl`	LEGaTO: Low-Energy, Secure, and Resilient Toolset for Heterogeneous Computing. CoRR Behzad Salami, Konstantinos Parasyris, Adrián Cristal, Osman S. Unsal, Xavier Martorell, Paul Carpenter, Raúl de la Cruz, Leonardo Bautista-Gomez, Daniel A. Jiménez, Carlos Álvarez, S. Nabavi, Sergi Madonar, Miquel Pericàs, Pedro Trancoso, Mustafa Abduljabbar, Jing Chen, Pirah Noor Soomro, Madhavan Manivannan, Micha vor dem Berge, Stefan Krupop, Frank Klawonn, Al Mekhlafi, Sigrun May, Tobias Becker, Georgi Gaydadjiev, Daniel Ödman, Hans Salomonsson, Devdatt P. Dubhashi, Oron Port, Yoav Etsion, Do Le Quoc, Christof Fetzer, Martin Kaiser, Nils Kucza, Jens Hagemeyer, René Griessl, Lennart Tigges, Kevin Mika, A. Hüffmeier, Th. Jungeblu, Marcelo Pasin, Valerio Schiavoni, Isabelly Rocha, Christian Göttel, Pascal Felber
2018	J	`jnl`	Global Dead-Block Management for Task-Parallel Programs. ACM Trans. Archit. Code Optim. Madhavan Manivannan, Miquel Pericàs, Vassilis Papaefstathiou, Per Stenström
2017	J	`jnl`	Runtime-Assisted Global Cache Management for Task-Based Parallel Programs. IEEE Comput. Archit. Lett. Madhavan Manivannan, Miquel Pericàs, Vassilis Papaefstathiou, Per Stenström
2016	A*	`conf`	RADAR: Runtime-assisted dead region management for last-level caches. HPCA Madhavan Manivannan, Vassilis Papaefstathiou, Miquel Pericàs, Per Stenström
2016	—	`—`	Towards Runtime-Assisted Cache Management for Task-Parallel Programs. Madhavan Manivannan
2014	A	`conf`	Runtime-Guided Cache Coherence Optimizations in Multi-core Architectures. IPDPS Madhavan Manivannan, Per Stenström
2013	B	`conf`	Efficient Forwarding of Producer-Consumer Data in Task-Based Programs. ICPP Madhavan Manivannan, Anurag Negi, Per Stenström
2011	B	`conf`	Implications of Merging Phases on Scalability of Multi-core Architectures. ICPP Madhavan Manivannan, Ben H. H. Juurlink, Per Stenström
2011	A	`conf`	Poster: implications of merging phases on scalability of multi-core architectures. ICS Madhavan Manivannan, Ben H. H. Juurlink, Per Stenström
2009	J	`jnl`	Towards modeling and integrated design automation of supercomputing clusters (MIDAS). Comput. Sci. Res. Dev. Nagarajan Venkateswaran, Aravind Vasudevan, Balaji Subramaniam, Ravindhiran Mukundrajan, T. P. Ramnath Sai Sagar, Madhavan Manivannan, Sriram Murali, Vinoth Krishnan Elangovan
2008	A	`conf`	On the concept of simultaneous execution of multiple applications on hierarchically based cluster and the silicon operating system. IPDPS N. Venkateswaran, Vinoth Krishnan Elangovan, Karthik Ganesan, TP Ramnath Sai Sagar, Sriram Aananthakrishanan, Shreyas Ramalingam, Shyamsundar Gopalakrishnan, Madhavan Manivannan, Deepak Srinivasan, Viswanath Krishnamurthy, Karthik Chandrasekar, Viswanath Venkatesan, Balaji Subramaniam, Vidya Sangkar L, Aravind Vasudevan, Shrikanth Ganapathy, Sriram Murali, Murali Thyagarajan
2007	J	`jnl`	Future generation supercomputers I: a paradigm for node architecture. SIGARCH Comput. Archit. News Nagarajan Venkateswaran, Deepak Srinivasan, Madhavan Manivannan, T. P. Ramnath Sai Sagar, Shyamsundar Gopalakrishnan, Vinoth Krishnan Elangovan, Karthik Chandrasekar, Prem Kumar Ramesh, Viswanath Venkatesan, Arvindakshan Babu, Sudharshan
2007	J	`jnl`	Future generation supercomputers II: a paradigm for cluster architecture. SIGARCH Comput. Archit. News Nagarajan Venkateswaran, Deepak Srinivasan, Madhavan Manivannan, T. P. Ramnath Sai Sagar, Shyamsundar Gopalakrishnan, Vinoth Krishnan Elangovan, Arvind M, Prem Kumar Ramesh, Karthik Ganesan, Viswanath Krishnamurthy, Sivaramakrishnan