Madhav P. Desai

48 papers A* 3B 3C 4Misc 16Journal 19Unranked 3
YearRankTypeTitle / Venue / Authors
2025 J jnl
Side-channel attacks and countermeasures for heart rate retrieval from ECG characterization device.
Int. J. Inf. Sec.
Pablo Pérez-Tirador, Madhav P. Desai, Alejandro Rodriguez, Elena Berral, Teresa Romero, Gabriel Caffarena, Ruzica Jevtic
2024 Misc conf
Efficient Parallel Simulation of Networked Synchronous Discrete-Event Systems.
WSC
Neha V. Karanjkar, Madhav P. Desai, Akhil Kushe, Anish Natekar
2023 J jnl
An evaluation of a microprocessor with two independent hardware execution threads coupled through a shared cache.
CoRR
Madhav P. Desai
2022 C conf
Sitar: A Cycle-based Discrete-Event Simulation Framework for Architecture Exploration.
SIMULTECH
Neha V. Karanjkar, Madhav P. Desai
2021 J jnl
An efficient reverse-lookup table based strategy for solving the synonym and cache coherence problem in virtually indexed, virtually tagged caches.
CoRR
Madhav P. Desai, Aniket Deshmukh
2018 J jnl
Quantification of the likelihood of single event multiple transients in logic circuits in bulk CMOS technology.
Microelectron. J.
Nanditha P. Rao, Madhav P. Desai
2017 J jnl
Neutron-induced strike: Study of multiple node charge collection in 14nm FinFETs.
CoRR
Nanditha P. Rao, Madhav P. Desai
2016 J jnl
Higher likelihood of multiple bit-flips due to neutron-induced strikes on logic gates.
CoRR
Nanditha P. Rao, Madhav P. Desai
2016 — conf
Low-Power, Low-Latency Hermite Polynomial Characterization of Heartbeats Using a Field-Programmable Gate Array.
IWBBIO
Kartik Lakhotia, Gabriel Caffarena, Alberto Gil, David G. Márquez, Abraham Otero, Madhav P. Desai
2016 J jnl
On Continuous-space Embedding of Discrete-parameter Queuing Systems.
CoRR
Neha V. Karanjkar, Madhav P. Desai
2016 J jnl
Projective cofactor decompositions of Boolean functions and the satisfiability problem.
CoRR
Madhav P. Desai, Virendra Sule
2015 C conf
A Detailed Characterization of Errors in Logic Circuits due to Single-Event Transients.
DSD
Nanditha P. Rao, Madhav P. Desai
2015 B conf
An Approach to Discrete Parameter Design Space Exploration of Multi-core Systems Using a Novel Simulation Based Interpolation Technique.
MASCOTS
Neha V. Karanjkar, Madhav P. Desai
2014 J jnl
Generalized cofactors and decomposition of Boolean satisfiability problems.
CoRR
Madhav P. Desai, Virendra Sule
2014 J jnl
Inner Loop Optimizations in Mapping Single Threaded Programs to Hardware.
CoRR
Madhav P. Desai
2014 J jnl
On the likelihood of multiple bit upsets in logic circuits.
CoRR
Nanditha P. Rao, Shahbaz Sarik, Madhav P. Desai
2014 J jnl
Optimization of Discrete-parameter Multiprocessor Systems using a Novel Ergodic Interpolation Technique.
CoRR
Neha V. Karanjkar, Madhav P. Desai
2012 — conf
The Click2NetFPGA Toolchain.
USENIX ATC
Teemu Rinta-aho, Mika Karlstedt, Madhav P. Desai
2010 C conf
A C-to-RTL Flow as an Energy Efficient Alternative to Embedded Processors in Digital Systems.
DSD
Sameer D. Sahasrabuddhe, Sreenivas Subramanian, Kunal P. Ghosh, Kavi Arya, Madhav P. Desai
2010 Misc conf
Bottleneck Identification Techniques Leading to Simplified Performance Models for Efficient Design Space Exploration in VLSI Memory Systems.
VLSI Design
Gautam Hazari, Madhav P. Desai, G. Srinivas
2010 J jnl
On Cycles in Random Graphs
CoRR
Madhav P. Desai
2009 B conf
Learning based address mapping for improving the performance of memory subsystems.
MASCOTS
Pratyush Kumar, Madhav P. Desai
2007 Misc conf
AHIR: A Hardware Intermediate Representation for Hardware Generation from High-level Programs.
VLSI Design
Sameer D. Sahasrabuddhe, Hakim Raja, Kavi Arya, Madhav P. Desai
2007 Misc conf
On the Impact of Address Space Assignment on Performance in Systems-on-Chip.
VLSI Design
Gautam Hazari, Madhav P. Desai, H. Kasture
2007 Misc conf
Parallelization of DC Analysis through Multiport Decomposition.
VLSI Design
Gaurav Trivedi, Madhav P. Desai, H. Narayanan
2006 Misc conf
Fast DC Analysis and Its Application to Combinatorial Optimization Problems.
VLSI Design
Gaurav Trivedi, Madhav P. Desai, H. Narayanan
2005 B conf
On Range Matrices and Wireless Networks in d Dimensions.
WiOpt
Madhav P. Desai, D. Manjunath
2005 Misc conf
Variance Reduction in Monte Carlo Capacitance Extraction.
VLSI Design
Shabbir H. Batterywala, Madhav P. Desai
2004 Misc conf
A Distributed and Pipelined Controller for a Modular and Scalable Hardware Emulator.
VLSI Design
Aditya Mittal, Madhav P. Desai
2004 Misc conf
A Novel Technique Towards Eliminating the Global Clock in VLSI Circuits.
VLSI Design
Gautam Hazari, Madhav P. Desai, Apoorv Gupta, Supratik Chakraborty
2004 Misc conf
On Buffering Schemes for Long Multi-Layer Nets.
VLSI Design
Vani Prasad, Madhav P. Desai
2003 Misc conf
Detailed Analysis of FIBL in MOS Transistors with High-K Gate Dielectrics.
VLSI Design
Nihar R. Mohapatra, Madhav P. Desai, V. Ramgopal Rao
2003 Misc conf
Interconnect Delay Minimization Using a Novel Pre-Mid-Post Buffer Strategy.
VLSI Design
Vani Prasad, Madhav P. Desai
2003 J jnl
Reconfigurable finite-state machine based IP lookup engine for high-speed router.
IEEE J. Sel. Areas Commun.
Madhav P. Desai, Ritu Gupta, Abhay Karandikar, Kshitiz Saxena, Vinayak Samant
2003 J jnl
The realization of finite state machines by decomposition and the principal lattice of partitions of a submodular function.
Discret. Appl. Math.
Madhav P. Desai, H. Narayanan, Sachin B. Patkar
2002 — conf
Impact of Technology Scaling on Metastability Performance of CMOS Synchronizing Latches.
ASP-DAC/VLSI Design
Maryam Shojaei Baghini, Madhav P. Desai
2002 J jnl
On the connectivity in finite ad hoc networks.
IEEE Commun. Lett.
Madhav P. Desai, D. Manjunath
2001 Misc conf
An On-Chip Coupling Capacitance Measurement Technique.
VLSI Design
Pratheep A. Nair, Anubhav Gupta, Madhav P. Desai
2001 Misc conf
Effect Of Fringing Capacitances In Sub 100 Nm Mosfet's With High-K Gate Dielectrics.
VLSI Design
Nihar R. Mohapatra, Arijit Dutta, Madhav P. Desai, V. Ramgopal Rao
2001 J jnl
Sub-100 nm CMOS circuit performance with high-K gate dielectrics.
Microelectron. Reliab.
Nihar R. Mohapatra, Arijit Dutta, G. Sridhar, Madhav P. Desai, V. Ramgopal Rao
2000 Misc conf
Inductance Characterization of Small Interconnects Using Test-Signal Method.
VLSI Design
Jeegar Tilak Shah, Madhav P. Desai, Sugata Sanyal
1999 Misc conf
A State Assignment Scheme Targeting Performance and Area.
VLSI Design
B. N. V. Malleswara Gupta, H. Narayanan, Madhav P. Desai
1999 C conf
Decomposition of Finite State Machines for Area, Delay Minimization.
ICCD
Rupesh S. Shelar, Madhav P. Desai, H. Narayanan
1998 A* conf
Robust Elmore Delay Models Suitable for Full Chip Timing Verification of a 600MHz CMOS Microprocessor.
DAC
Nevine Nassif, Madhav P. Desai, Dale H. Hall
1996 A* conf
A Systematic Technique for Verifying Critical Path Delays in a 300MHz Alpha CPU Design Using Circuit Simulation.
DAC
Madhav P. Desai, Yao-Tsung Yen
1996 A* conf
Sizing of Clock Distribution Networks for High Performance CPU Chips.
DAC
Madhav P. Desai, Radenko Cvijetic, James Jensen
1994 J jnl
A characterization of the smallest eigenvalue of a graph.
J. Graph Theory
Madhav P. Desai, Vasant B. Rao
1993 J jnl
On the Convergence of Reversible Markov Chains.
SIAM J. Matrix Anal. Appl.
Madhav P. Desai, Vasant B. Rao