Maciej J. Ciesielski

115 papers A* 9A 23B 3C 14Misc 5Journal 32Unranked 29

Year	Rank	Type	Title / Venue / Authors
2026	Misc	`conf`	Universal Formal Verification Approach for Modular Reduction Circuits. VLSID Jiteshri Dasari, Maciej J. Ciesielski
2024	A	`conf`	Combining Formal Verification and Testing for Debugging of Arithmetic Circuits. DATE Jiteshri Dasari, Maciej J. Ciesielski
2024	C	`conf`	Linear Algebra Approach to Verification of Modular $(2^{n}-1)$ Multipliers. VLSI-SoC Jiteshri Dasari, Cunxi Yu, Maciej J. Ciesielski
2024	—	`conf`	Verification and Debugging of Modular (2 VLSI-SoC (Selected Papers) Jiteshri Dasari, Cunxi Yu, Maciej J. Ciesielski
2023	A	`conf`	Efficient Formal Verification and Debugging of Arithmetic Divider Circuits. ICCAD Jiteshri Dasari, Maciej J. Ciesielski
2023	C	`conf`	Formal Methods in Arithmetic Circuit Verification: A Brief History and Look into the Future. DSD Maciej J. Ciesielski
2023	—	`conf`	Formal Verification of Divider Circuits by Hardware Reduction. SMACD Atif Yasin, Tiankai Su, Sébastien Pillement, Maciej J. Ciesielski
2023	A*	`conf`	Formal Verification of Restoring Dividers made Fast and Simple. DAC Jiteshri Dasari, Maciej J. Ciesielski
2022	C	`conf`	Functional Verification of Arithmetic Circuits: Survey of Formal Methods. DDECS Maciej J. Ciesielski, Atif Yasin, Jiteshri Dasari
2020	—	`conf`	Dual Approach to Solving SAT in Hardware. DTIS Dinesh D. Narasimharaju, R. S. Suraj Rao, Akshaya Sandeep Waingade, Atif Yasin, Maciej J. Ciesielski
2020	—	`conf`	Formal Verification of Constrained Arithmetic Circuits using Computer Algebraic Approach. ISVLSI Tiankai Su, Atif Yasin, Sébastien Pillement, Maciej J. Ciesielski
2020	A	`conf`	SPEAR: Hardware-based Implicit Rewriting for Square-root Circuit Verification. DATE Atif Yasin, Tiankai Su, Sébastien Pillement, Maciej J. Ciesielski
2020	J	`jnl`	Understanding Algebraic Rewriting for Arithmetic Circuit Verification: A Bit-Flow Model. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Maciej J. Ciesielski, Tiankai Su, Atif Yasin, Cunxi Yu
2019	J	`jnl`	Formal Analysis of Galois Field Arithmetic Circuits-Parallel Verification and Reverse Engineering. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Cunxi Yu, Maciej J. Ciesielski
2019	—	`conf`	Formal Verification of Integer Dividers: Division by a Constant. ISVLSI Atif Yasin, Tiankai Su, Sébastien Pillement, Maciej J. Ciesielski
2019	C	`conf`	Functional Verification of Hardware Dividers using Algebraic Model. VLSI-SoC Atif Yasin, Tiankai Su, Sébastien Pillement, Maciej J. Ciesielski
2019	J	`jnl`	Spectral Approach to Verifying Non-linear Arithmetic Circuits. CoRR Cunxi Yu, Tiankai Su, Atif Yasin, Maciej J. Ciesielski
2019	—	`conf`	Spectral approach to verifying non-linear arithmetic circuits. ASP-DAC Cunxi Yu, Tiankai Su, Atif Yasin, Maciej J. Ciesielski
2018	C	`conf`	Computer Algebraic Approach to Verification and Debugging of Galois Field Multipliers. ISCAS Tiankai Su, Atif Yasin, Cunxi Yu, Maciej J. Ciesielski
2018	—	`conf`	End-to-End Industrial Study of Retiming. ISVLSI Cunxi Yu, Chau-Chin Huang, Gi-Joon Nam, Mihir Choudhury, Victor N. Kravets, Andrew Sullivan, Maciej J. Ciesielski, Giovanni De Micheli
2018	J	`jnl`	Fast Algebraic Rewriting Based on And-Inverter Graphs. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Cunxi Yu, Maciej J. Ciesielski, Alan Mishchenko
2018	J	`jnl`	Formal Analysis of Galois Field Arithmetics - Parallel Verification and Reverse Engineering. CoRR Cunxi Yu, Maciej J. Ciesielski
2018	B	`conf`	Rewriting Environment for Arithmetic Circuit Verification. LPAR Cunxi Yu, Atif Yasin, Tiankai Su, Alan Mishchenko, Maciej J. Ciesielski
2017	J	`jnl`	Advanced Datapath Synthesis using Graph Isomorphism. CoRR Cunxi Yu, Mihir Choudhury, Andrew Sullivan, Maciej J. Ciesielski
2017	A	`conf`	Advanced datapath synthesis using graph isomorphism. ICCAD Cunxi Yu, Mihir Choudhury, Andrew Sullivan, Maciej J. Ciesielski
2017	—	`conf`	Efficient parallel verification of Galois field multipliers. ASP-DAC Cunxi Yu, Maciej J. Ciesielski
2017	—	`conf`	Formal Verification of Truncated Multipliers Using Algebraic Approach and Re-Synthesis. ISVLSI Tiankai Su, Cunxi Yu, Atif Yasin, Maciej J. Ciesielski
2017	J	`jnl`	Incremental SAT-Based Reverse Engineering of Camouflaged Logic Circuits. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Cunxi Yu, Xiangyu Zhang, Duo Liu, Maciej J. Ciesielski, Daniel E. Holcomb
2017	A	`conf`	Reverse engineering of irreducible polynomials in GF(2 DATE Cunxi Yu, Daniel E. Holcomb, Maciej J. Ciesielski
2016	—	`conf`	Analyzing Imprecise Adders Using BDDs - A Case Study. ISVLSI Cunxi Yu, Maciej J. Ciesielski
2016	C	`conf`	Automatic word-level abstraction of datapath. ISCAS Cunxi Yu, Maciej J. Ciesielski
2016	A*	`conf`	DAG-aware logic synthesis of datapaths. DAC Cunxi Yu, Maciej J. Ciesielski, Mihir Choudhury, Andrew Sullivan
2016	J	`jnl`	Efficient Parallel Verification of Galois Field Multipliers. CoRR Cunxi Yu, Maciej J. Ciesielski
2016	—	`conf`	Formal Verification Using Don't-Care and Vanishing Polynomials. ISVLSI Cunxi Yu, Maciej J. Ciesielski
2016	J	`jnl`	Formal Verification of Arithmetic Circuits by Function Extraction. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Cunxi Yu, Walter Brown, Duo Liu, André Rossi, Maciej J. Ciesielski
2016	J	`jnl`	Reverse Engineering of Irreducible Polynomials in GF(2^m) Arithmetic. CoRR Cunxi Yu, Daniel E. Holcomb, Maciej J. Ciesielski
2015	—	`conf`	Exploiting Circuit Duality to Speed up SAT. ISVLSI Luca Gaetano Amarù, Pierre-Emmanuel Gaillardon, Alan Mishchenko, Maciej J. Ciesielski, Giovanni De Micheli
2015	—	`conf`	Logic Debugging of Arithmetic Circuits. ISVLSI Samaneh Ghandali, Cunxi Yu, Duo Liu, Walter Brown, Maciej J. Ciesielski
2015	C	`conf`	Verification of arithmetic datapath designs using word-level approach - A case study. ISCAS Cunxi Yu, Walter Brown, Maciej J. Ciesielski
2015	A*	`conf`	Verification of gate-level arithmetic circuits by function extraction. DAC Maciej J. Ciesielski, Cunxi Yu, Walter Brown, Duo Liu, André Rossi
2014	A	`conf`	Fast STA prediction-based gate-level timing simulation. DATE Tariq B. Ahmad, Maciej J. Ciesielski
2014	C	`conf`	Fast time-parallel C-based event-driven RTL simulation. DDECS Tariq Bashir Ahmad, Maciej J. Ciesielski
2014	—	`conf`	Function Extraction from Arithmetic Bit-Level Circuits. ISVLSI Maciej J. Ciesielski, Walter Brown, Duo Liu, André Rossi
2014	—	`conf`	Parallel Multi-core Verilog HDL Simulation Using Domain Partitioning. ISVLSI Tariq B. Ahmad, Maciej J. Ciesielski
2013	—	`conf`	An Approach to Multi-core Functional Gate-Level Simulation Minimizing Synchronization and Communication Overheads. MTV Tariq Bashir Ahmad, Maciej J. Ciesielski
2013	—	`conf`	Arithmetic Bit-Level Verification Using Network Flow Model. Haifa Verification Conference Maciej J. Ciesielski, Walter Brown, André Rossi
2013	A	`conf`	FPGA latency optimization using system-level transformations and DFG restructuring. DATE Daniel Gomez-Prado, Maciej J. Ciesielski, Russell Tessier
2013	J	`jnl`	MULTES: Multilevel Temporal-Parallel Event-Driven Simulation. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Dusung Kim, Maciej J. Ciesielski, Seiyang Yang
2011	J	`jnl`	A Variation-Aware Taylor Expansion Diagram-Based Approach for Nano-CMOS Register-Transfer Level Leakage Optimization. J. Low Power Electron. Shibaji Banerjee, Jimson Mathew, Saraju P. Mohanty, Dhiraj K. Pradhan, Maciej J. Ciesielski
2011	A	`conf`	A new distributed event-driven gate-level HDL simulation by accurate prediction. DATE Dusung Kim, Maciej J. Ciesielski, Seiyang Yang
2011	B	`conf`	Algebraic approach to arithmetic design verification. FMCAD Mohamed Abdul Basith, Tariq B. Ahmad, André Rossi, Maciej J. Ciesielski
2011	A	`conf`	Temporal parallel simulation: A fast gate-level HDL simulation using higher level models. DATE Dusung Kim, Maciej J. Ciesielski, Kyuho Shim, Seiyang Yang
2011	Misc	`conf`	Variation-Aware TED-Based Approach for Nano-CMOS RTL Leakage Optimization. VLSI Design Shibaji Banerjee, Jimson Mathew, Dhiraj K. Pradhan, Saraju P. Mohanty, Maciej J. Ciesielski
2010	—	`conf`	Retiming arithmetic datapaths using Timed Taylor Expansion Diagrams. HLDVT Daniel Gomez-Prado, Dusung Kim, Maciej J. Ciesielski, Emmanuel Boutillon
2010	J	`jnl`	The best constant approximant operators in Lorentz spaces Gamma J. Approx. Theory Maciej J. Ciesielski, Anna Kaminska
2009	J	`jnl`	High-Level Dataflow Transformations Using Taylor Expansion Diagrams. IEEE Des. Test Comput. Maciej J. Ciesielski, Jérémie Guillot, Daniel Gomez-Prado, Emmanuel Boutillon
2009	J	`jnl`	Optimization of Data-Flow Computations Using Canonical TED Representation. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Maciej J. Ciesielski, Daniel Gomez-Prado, Qian Ren, Jérémie Guillot, Emmanuel Boutillon
2009	A	`conf`	Optimizing data flow graphs to minimize hardware implementation. DATE Daniel Gomez-Prado, Qian Ren, Maciej J. Ciesielski, Jérémie Guillot, Emmanuel Boutillon
2008	—	`conf`	A fast two-pass HDL simulation with on-demand dump. ASP-DAC Kyuho Shim, Young-Rae Cho, Namdo Kim, Hyuncheol Baik, Kyungkuk Kim, Dusung Kim, Jaebum Kim, Byeongun Min, Kyumyung Choi, Maciej J. Ciesielski, Seiyang Yang
2008	Misc	`conf`	Simulation Acceleration with HW Re-Compilation Avoidance. VLSI Design Kyuho Shim, Kesava R. Talupuru, Maciej J. Ciesielski, Seiyang Yang
2008	—	`conf`	Temporal parallel gate-level timing simulation. HLDVT Dusung Kim, Maciej J. Ciesielski, Kyuho Shim, Seiyang Yang
2007	A	`conf`	Data-flow transformations using Taylor expansion diagrams. DATE Maciej J. Ciesielski, Serkan Askar, Daniel Gomez-Prado, Jérémie Guillot, Emmanuel Boutillon
2006	A	`conf`	Efficient factorization of DSP transforms using taylor expansion diagrams. DATE Jérémie Guillot, Emmanuel Boutillon, Qian Ren, Maciej J. Ciesielski, Daniel Gomez-Prado, Serkan Askar
2006	J	`jnl`	Taylor Expansion Diagrams: A Canonical Representation for Verification of Data Flow Designs. IEEE Trans. Computers Maciej J. Ciesielski, Priyank Kalla, Serkan Askar
2005	—	`conf`	An ILP Formulation for Yield-driven Architectural Synthesis. DFT Zhaojun Wo, Israel Koren, Maciej J. Ciesielski
2005	B	`conf`	Design validation of behavioral VHDL descriptions for arbitrary fault models. ETS Fei Xin, Maciej J. Ciesielski, Ian G. Harris
2005	J	`jnl`	Functional test generation based on word-level SAT. J. Syst. Archit. Zhihong Zeng, Kesava R. Talupuru, Maciej J. Ciesielski
2005	C	`conf`	Yield-aware Floorplanning. DSD Zhaojun Wo, Israel Koren, Maciej J. Ciesielski
2004	A*	`conf`	A new state assignment technique for testing and low power. DAC Sungju Park, Sangwook Cho, Seiyang Yang, Maciej J. Ciesielski
2004	—	`conf`	Algorithms for Taylor Expansion Diagrams. ISMVL Görschwin Fey, Rolf Drechsler, Maciej J. Ciesielski
2004	—	`conf`	Variable ordering for taylor expansion diagrams. HLDVT Daniel Gomez-Prado, Qian Ren, Serkan Askar, Maciej J. Ciesielski, Emmanuel Boutillon
2003	A	`conf`	Fast Computation of Data Correlation Using BDDs. DATE Zhihong Zeng, Qiushuang Zhang, Ian G. Harris, Maciej J. Ciesielski
2003	—	`conf`	Mathematical framework for representing discrete functions as word-level polynomials. HLDVT Dhiraj K. Pradhan, Serkan Askar, Maciej J. Ciesielski
2002	J	`jnl`	A comprehensive approach to the partial scan problem using implicitstate enumeration. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Priyank Kalla, Maciej J. Ciesielski
2002	J	`jnl`	Analytical approach to layout generation of datapath cells. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Maciej J. Ciesielski, Serkan Askar, Samuel Levitin
2002	J	`jnl`	BDS: a BDD-based logic optimization system. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Congguang Yang, Maciej J. Ciesielski
2002	—	`conf`	High-level design verification using Taylor Expansion Diagrams: first results. HLDVT Priyank Kalla, Maciej J. Ciesielski, Emmanuel Boutillon, Eric Martin
2002	A	`conf`	Taylor Expansion Diagrams: A Compact, Canonical Representation with Applications to Symbolic Verification. DATE Maciej J. Ciesielski, Priyank Kalla, Zhihong Zeng, Bruno Rouzeyre
2001	C	`conf`	Functional Test Generation using Constraint Logic Programming. VLSI-SOC Zhihong Zeng, Maciej J. Ciesielski, Bruno Rouzeyre
2001	A	`conf`	LPSAT: a unified approach to RTL satisfiability. DATE Zhihong Zeng, Priyank Kalla, Maciej J. Ciesielski
2001	J	`jnl`	Strategies for solving the Boolean satisfiability problem using binary decision diagrams. J. Syst. Archit. Priyank Kalla, Zhihong Zeng, Maciej J. Ciesielski
2001	—	`conf`	Taylor expansion diagrams: a new representation for RTL verification. HLDVT Maciej J. Ciesielski, Priyank Kalla, Zhihong Zeng, Bruno Rouzeyre
2000	A	`conf`	A BDD-Based Satisfiability Infrastructure Using the Unate Recursive Paradigm. DATE Priyank Kalla, Zhihong Zeng, Maciej J. Ciesielski, ChiLai Huang
2000	A*	`conf`	BDS: a BDD-based logic optimization system. DAC Congguang Yang, Maciej J. Ciesielski, Vigyan Singhal
2000	J	`jnl`	Retiming-based factorization for sequential logic optimization. ACM Trans. Design Autom. Electr. Syst. Surendra Bommu, Niall O'Neill, Maciej J. Ciesielski
2000	A	`conf`	Synthesis for Mixed CMOS/PTl Logic. DATE Congguang Yang, Maciej J. Ciesielski
1999	A	`conf`	Analytical approach to custom datapath design. ICCAD Serkan Askar, Maciej J. Ciesielski
1999	C	`conf`	BDD Decomposition for Efficient Logic Synthesis. ICCD Congguang Yang, Maciej J. Ciesielski, Vigyan Singhal
1999	A	`conf`	Performance Driven Resynthesis by Exploiting Retiming-Induced State Register Equivalence. DATE Priyank Kalla, Maciej J. Ciesielski
1999	—	`conf`	Transistor level placement for full custom datapath cell design. ISPD Durgam Vahia, Maciej J. Ciesielski
1998	A	`conf`	A comprehensive approach to the partial scan problem using implicit state enumeration. ITC Priyank Kalla, Maciej J. Ciesielski
1998	A	`conf`	Reencoding for cycle-time minimization under fixed encoding length. ICCAD Balakrishnan Iyer, Maciej J. Ciesielski
1998	J	`jnl`	Wave-pipelining: a tutorial and research survey. IEEE Trans. Very Large Scale Integr. Syst. Wayne P. Burleson, Maciej J. Ciesielski, Fabian Klass, W. Liu
1997	—	`conf`	Intelligent Simulation for Computer Aided Design of Optical Networks. ONDM Imrich Chlamtac, Maciej J. Ciesielski, Andrea Fumagalli, Chester A. Ruszczyk, Gosse Wedzinga
1997	Misc	`conf`	Testability of Sequential Circuits with Multi-Cycle False Path. VTS Priyank Kalla, Maciej J. Ciesielski
1996	A	`conf`	Metamorphosis: state assignment by retiming and re-encoding. ICCAD Balakrishnan Iyer, Maciej J. Ciesielski
1995	—	`conf`	Elimination of multi-cycle false paths by state encoding. ED&TC Zafar Hasan, Maciej J. Ciesielski
1995	J	`jnl`	FSM Decomposition and Functional Verification of FSM Networks. VLSI Design Zafar Hasan, Maciej J. Ciesielski
1994	C	`conf`	Forum: Wave-pipelining: Is it Practical? ISCAS Wayne P. Burleson, Leonard W. Cotten, Fabian Klass, Maciej J. Ciesielski
1993	J	`jnl`	Clock period minimization with wave pipelining. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Donald A. Joy, Maciej J. Ciesielski
1993	Misc	`conf`	Functional verification and simulation of FSM networks. VTS Zafar Hasan, Maciej J. Ciesielski
1992	J	`jnl`	A Fast Partitioning Method for PLA-Based FPGAs. IEEE Des. Test Comput. Zafar Hasan, David Harrison, Maciej J. Ciesielski
1992	C	`conf`	Finite State Machine Decomposition Using Multiway Partitioning. ICCD Maya K. Yajnik, Maciej J. Ciesielski
1992	J	`jnl`	Layer assignment for printed circuit boards and integrated circuits. Proc. IEEE Donald A. Joy, Maciej J. Ciesielski
1992	J	`jnl`	PLADE: a two-stage PLA decomposition. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Maciej J. Ciesielski, Seiyang Yang
1991	A*	`conf`	A Unified Approach to Input-Output Encoding for FSM State Assignment. DAC Maciej J. Ciesielski, Jia-Jye Shen, Marc Davio
1991	J	`jnl`	Optimum and suboptimum algorithms for input encoding and its relationship to logic minimization. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Seiyang Yang, Maciej J. Ciesielski
1991	A*	`conf`	Placement for Clock Period Minimization With Multiple Wave Propagation. DAC Donald A. Joy, Maciej J. Ciesielski
1989	J	`jnl`	Layer assignment for VLSI interconnect delay minimization. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Maciej J. Ciesielski
1989	C	`conf`	Multiple-valued Boolean minimization based on graph coloring. ICCD Maciej J. Ciesielski, Saeyang Yang, Marek A. Perkowski
1989	A	`conf`	PLA decomposition with generalized decoders. ICCAD Seiyang Yang, Maciej J. Ciesielski
1987	J	`jnl`	Digraph Relaxation for 2-Dimensional Placement of IC Blocks. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Maciej J. Ciesielski, Edwin Kinnen
1985	J	`jnl`	Two-Dimensional Routing for the Silc Silicon Compiler. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Maciej J. Ciesielski
1982	A*	`conf`	An analytical method for compacting routing area in integrated circuits. DAC Maciej J. Ciesielski, Edwin Kinnen
1981	A*	`conf`	An optimum layer assignment for routing in ICs and PCBs. DAC Maciej J. Ciesielski, Edwin Kinnen