Maciej Bellos

13 papers C 1Misc 3Journal 2Unranked 6
YearRankTypeTitle / Venue / Authors
2006 J jnl
A core generator for arithmetic cores and testing structures with a network interface.
J. Syst. Archit.
Dimitris Bakalis, Kostas Adaos, Dimitrios Lymperopoulos, Maciej Bellos, Haridimos T. Vergos, George Alexiou, Dimitris Nikolos
2005 Misc conf
Deterministic Test Vector Compression / Decompression Using an Embedded Processor.
EDCC
Maciej Bellos, Dimitris Nikolos
2005 — —
Τεχνικές ελέγχου ορθής λειτουργίας με έμφαση στη χαμηλή κατανάλωση ισχύος
Maciej Bellos
2004 — conf
An Efficient Test Vector Ordering Method for Low Power Testing.
ISVLSI
Xrysovalantis Kavousianos, Dimitris Bakalis, Maciej Bellos, Dimitris Nikolos
2004 — conf
Low Power Testing by Test Vector Ordering with Vector Repetition.
ISQED
Maciej Bellos, Dimitris Bakalis, Dimitris Nikolos, Xrysovalantis Kavousianos
2004 — conf
Scan Cell Ordering for Low Power BIST.
ISVLSI
Maciej Bellos, Dimitris Bakalis, Dimitris Nikolos
2003 C conf
DV-TSE: Difference Vector Based Test Set Embedding.
VLSI-SOC
Maciej Bellos, Xrysovalantis Kavousianos, Dimitris Nikolos, Dimitri Kagaris
2003 J jnl
Deterministic BIST for RNS Adders.
IEEE Trans. Computers
Haridimos T. Vergos, Dimitris Nikolos, Maciej Bellos, Costas Efstathiou
2003 — conf
Low Power Test Set Embedding Based on Phase Shifters.
ISVLSI
Maciej Bellos, Dimitri Kagaris, Dimitris Nikolos
2002 Misc conf
Test Set Embedding Based on Phase Shifters.
EDCC
Maciej Bellos, Dimitrios Kagaris, Dimitris Nikolos
2001 — conf
A Formal Test Set for RNS Adders and an Efficient Low Power BIST Scheme.
LATW
Haridimos T. Vergos, Dimitris Nikolos, Maciej Bellos, Costas Efstathiou
1999 Misc conf
Path Delay Fault Testing of a Class of Circuit-Switched Multistage Interconnection Networks.
EDCC
Maciej Bellos, Dimitris Nikolos, Haridimos T. Vergos
1999 — conf
Path delay fault testing of Benes multistage interconnection networks.
ICECS
Haridimos T. Vergos, Maciej Bellos, Dimitris Nikolos