Maarten Vertregt

21 papers A 3C 1Journal 8Unranked 9

Year	Rank	Type	Title / Venue / Authors
2016	A	`conf`	Circuit valorization in the IC design ecosystem. ICCAD José Pineda de Gyvez, Hamed Fatemi, Maarten Vertregt
2014	J	`jnl`	Digital Systems Power Management for High Performance Mixed Signal Platforms. IEEE Trans. Circuits Syst. I Regul. Pap. Ajay Kapoor, Cas Groot, Gerard Villar Pique, Hamed Fatemi, Juan Diego Echeverri, Leo Sevat, Maarten Vertregt, Maurice Meijer, Vibhu Sharma, Yu Pu, José Pineda de Gyvez
2014	A	`conf`	Standard cell library tuning for variability tolerant designs. DATE Sebastien Fabrie, Juan Diego Echeverri, Maarten Vertregt, José Pineda de Gyvez
2011	—	`conf`	A narrow-to-wideband scrambling technique increasing software radio receiver linearity. ESSCIRC Fabian van Houwelingen, Ed van Tuijl, Bram Nauta, Maarten Vertregt
2010	C	`conf`	A forward body bias generator for digital CMOS circuits with supply voltage scaling. ISCAS Maurice Meijer, José Pineda de Gyvez, Ben Kup, Bert van Uden, Peter Bastiaansen, Marco Lammers, Maarten Vertregt
2010	—	`conf`	High performance mixed signal: Business and technology. ESSCIRC René Penning de Vries, Hans Rijns, Maarten Vertregt
2009	—	`conf`	A 0.45pJ/conv-step 1.2Gs/s 6b full-Nyquist non-calibrated flash ADC in 45nm CMOS and its scaling behavior. ESSCIRC Paul Veldhorst, George Goksun, Anne-Johan Annema, Bram Nauta, Berry A. J. Buter, Maarten Vertregt
2009	J	`jnl`	A 1.2-V 250-mW 14-b 100-MS/s Digitally Calibrated Pipeline ADC in 90-nm CMOS. IEEE J. Solid State Circuits Hans Van de Vel, Berry A. J. Buter, Hendrik van der Ploeg, Maarten Vertregt, Govert J. G. M. Geelen, Edward J. F. Paulus
2008	J	`jnl`	A 1.35 GS/s, 10 b, 175 mW Time-Interleaved AD Converter in 0.13 µm CMOS. IEEE J. Solid State Circuits Simon M. Louwsma, A. J. M. van Tuijl, Maarten Vertregt, Bram Nauta
2007	—	`conf`	A Time-Interleaved Track & hold in 0.13 μm CMOS sub-sampling a 4 GHz signal with 43 dB SNDR. CICC Simon M. Louwsma, Ed van Tuijl, Maarten Vertregt, Bram Nauta
2006	J	`jnl`	A 15-bit 30-MS/s 145-mW three-step ADC for imaging applications. IEEE J. Solid State Circuits Hendrik van der Ploeg, Maarten Vertregt, Marco Lammers
2005	—	`conf`	A 15-bit 30 MS/s 145 mW three-step ADC for imaging applications. ESSCIRC Hendrik van der Ploeg, Maarten Vertregt, Marco Lammers
2005	A	`conf`	Systematic power reduction and performance analysis of mismatch limited ADC designs. ISLPED Peter C. S. Scholtens, David Smola, Maarten Vertregt
2004	—	`conf`	A 1.6 GS/s, 16 times interleaved track & hold with 7.6 ENOB in 0.12 μm CMOS [ADC applications]. ESSCIRC Simon M. Louwsma, Ed J. M. van Tuijl, Maarten Vertregt, Peter C. S. Scholtens, Bram Nauta
2004	—	`conf`	Assessment of the merits of CMOS technology scaling for analog circuit design. ESSCIRC Maarten Vertregt, Peter C. S. Scholtens
2003	—	`conf`	A 1.8V 100mW 12-bits 80Msample/s two-step ADC in 0.18-μm CMOS. ESSCIRC Amir Zjajo, Hendrik van der Ploeg, Maarten Vertregt
2002	J	`jnl`	A 6-b 1.6-Gsample/s flash ADC in 0.18-μm CMOS using averaging termination. IEEE J. Solid State Circuits Peter C. S. Scholtens, Maarten Vertregt
2001	J	`jnl`	A 2.5-V 12-b 54-Msample/s 0.25-μm CMOS ADC in 1-mm IEEE J. Solid State Circuits Hendrik van der Ploeg, Gian Hoogzaad, Henk A. H. Termeer, Maarten Vertregt, Raf L. J. Roovers
2001	J	`jnl`	A Mixed-Signal Design Roadmap. IEEE Des. Test Comput. Ralf Brederlow, Werner Weber, Joseph Sauerer, Stéphane Donnay, Piet Wambacq, Maarten Vertregt
1996	—	`conf`	BiCMOS and CMOS: a long term relation. ICECS Marcel J. M. Pelgrom, Maarten Vertregt
1994	J	`jnl`	A 25-Ms/s 8-bit CMOS A/D converter for embedded application. IEEE J. Solid State Circuits Marcel J. M. Pelgrom, A. C. Jeannet v. Rens, Maarten Vertregt, Marcel B. Dijkstra