M. S. Bhat - RankMe

29 papers C 1Misc 2Journal 13Unranked 13

Year	Rank	Type	Title / Venue / Authors
2024	J	`jnl`	Optimized Compressed Sensing for IoT: Advanced Algorithms for Efficient Sparse Signal Reconstruction in Edge Devices. IEEE Access Ramachandra Gambheer, M. S. Bhat
2023	J	`jnl`	CCD Sensor Based Cameras for Sustainable Streaming IoT Applications With Compressed Sensing. IEEE Access Ramachandra Gambheer, M. S. Bhat
2021	J	`jnl`	A fully differential switched-capacitor integrator based programmable resolution hybrid ADC architecture for biomedical applications. IET Circuits Devices Syst. Sreenivasulu Polineni, S. Rekha, M. S. Bhat
2020	J	`jnl`	A 0.3-V, 2.4-nW, and 100-Hz fourth-order LPF for ECG signal processing. Int. J. Circuit Theory Appl. G. Hanumantha Rao, Sreenivasulu Polineni, S. Rekha, M. S. Bhat
2020	J	`jnl`	A Switched Capacitor-Based SAR ADC Employing a Passive Reference Charge Sharing and Charge Accumulation Technique. Circuits Syst. Signal Process. Sreenivasulu Polineni, M. S. Bhat, S. Rekha
2019	J	`jnl`	A 0.3 V, 56 dB DR, 100 Hz fourth order low-pass filter for ECG acquisition system. Microelectron. J. Sreenivasulu Polineni, G. Hanumanta Rao, S. Rekha, M. S. Bhat
2019	—	`conf`	Design of High Resolution Delta Sigma Modulator in 180 nm CMOS technology. ISED Samarth Bonthala, Yashas Uppoor, Ashika Nayak, Sreenivasulu Polineni, M. S. Bhat
2018	J	`jnl`	Fabrication and characterisation of RF MEMS capacitive switches tuned for X and Ku bands. Int. J. Mechatronics Autom. E. S. Shajahan, M. S. Bhat
2018	—	`conf`	High Isolation Single Pole Four Throw RF MEMS Switches for X band. ISED E. S. Shajahan, M. S. Bhat
2017	—	`conf`	Design of high performance dual-gate nano-scale In0.55Ga0.45 as transistor with modified substrate geometry. UEMCON Baldeo Sharan Sharma, M. S. Bhat
2017	J	`jnl`	Triple Reduced Surface Field Drain Extended MOS Device Design and Its RF Performance Evaluation for Sub-Micron RF SoC Platform. J. Low Power Electron. B. Jhnanesh Somayaji, M. S. Bhat
2016	—	`conf`	Analysis of implant parameters in high voltage TRIPLE RESURF LDMOS for advanced SoC applications. ISED B. Jhnanesh Somayaji, M. S. Bhat
2016	—	`conf`	Smart handheld platform for electrochemical bio sensors. VDAT Suraj Hebbar, Vinay Kumar, M. S. Bhat, Navakanta Bhat
2015	J	`jnl`	Low Energy and Area Efficient Nonbinary Capacitor Array Based Successive Approximation Register Analog-to-Digital Converter. J. Low Power Electron. D. N. Jagadish, M. S. Bhat
2014	—	`conf`	A Low Voltage Inverter Based Differential Amplifier for Low Power Switched Capacitor Applications. ISED D. N. Jagadish, M. S. Bhat
2014	J	`jnl`	A nonlinear level set model for image deblurring and denoising. Vis. Comput. A. A. Bini, M. S. Bhat
2014	—	`conf`	Design of a triple band-notched circular monopole antenna for UWB applications. WOCN B. Chenna Reddy, E. S. Shajahan, M. S. Bhat
2014	J	`jnl`	Despeckling low SNR, low contrast ultrasound images via anisotropic level set diffusion. Multidimens. Syst. Signal Process. A. A. Bini, M. S. Bhat
2014	—	`conf`	GSM and GUI Based Remote Data Logging System. ISED Sadeque Reza Khan, Rajsekhar Kr. Nath, M. S. Bhat
2014	—	`conf`	Inductive Tuned High Isolation RF MEMS Capacitive Shunt Switches. ISED E. S. Shajahan, M. S. Bhat, B. Chenna Reddy
2014	—	`conf`	Low Energy and Area Efficient Nonbinary Capacitor Array Based SAR ADC. ISED D. N. Jagadish, M. S. Bhat
2013	C	`conf`	Object detection and obstacle avoidance for mobile robot using stereo camera. CCA R. Lagisetty, N. K. Philip, R. Padhi, M. S. Bhat
2012	J	`jnl`	Minimization of Via-Induced Signal Reflection in On-Chip High Speed Interconnect Lines. Circuits Syst. Signal Process. K. Soorya Krishna, M. S. Bhat
2009	J	`jnl`	Design of resolution adaptive TIQ flash ADC using AMS 0.35 µm technology. Int. J. Inf. Commun. Technol. G. Rajashekar, M. S. Bhat
2006	Misc	`conf`	Extrinsic Analog Synthesis Using Piecewise Linear Current-Mode Circuits. VLSI Design M. S. Bhat, S. Rekha, H. S. Jamadagni
2005	—	`conf`	An Extrinsic Method for the Synthesis of Analog Functions using Non-Linear Current-Mode Circuits. IICAI M. S. Bhat, S. Rekha, H. S. Jamadagni
2005	—	`conf`	An Extrinsic Method of Evolutionary Synthesis of Multiple-Valued Arithmetic Functions using Genetic Algorithms. IICAI M. S. Bhat, S. Rekha, H. S. Jamadagni
2005	Misc	`conf`	Power Optimization in Current Mode Circuits. VLSI Design M. S. Bhat, H. S. Jamadagni
2005	—	`conf`	Static power minimization in current-mode circuits. ASP-DAC M. S. Bhat, H. S. Jamadagni