M. Ray Mercer - RankMe

72 papers A* 12A 26C 5Misc 6Journal 12Unranked 11

Year	Rank	Type	Title / Venue / Authors
2005	A	`conf`	An optimal test pattern selection method to improve the defect coverage. ITC Yuxin Tian, Michael R. Grimaila, Weiping Shi, M. Ray Mercer
2004	—	`conf`	A Preliminary Investigation of Observation Diversity for Enhancing Fortuitous Detection of Defects. DFT Jennifer Dworak, James Wingfield, M. Ray Mercer
2004	A	`conf`	Balanced Excitation and Its Effect on the Fortuitous Detection of Dynamic Defects. DATE Jennifer Dworak, Brad Cobb, James Wingfield, M. Ray Mercer
2004	Misc	`conf`	Excitation, Observation, and ELF-MD: Optimization Criteria for High Quality Test Sets. VTS Jennifer Dworak, David Dorsey, Amy Wang, M. Ray Mercer
2003	—	`conf`	Function-Based Dynamic Compaction and its Impact on Test Set Sizes. DFT James Wingfield, Jennifer Dworak, M. Ray Mercer
2003	—	`conf`	Minimizing Defective Part Level Using a Linear Programming-Based Optimal Test Selection Method. Asian Test Symposium Yuxin Tian, Michael R. Grimaila, Weiping Shi, M. Ray Mercer
2003	A	`conf`	Using Logic Models To Predict The Detection Behavior Of Statistical Timing Defects. ITC Li-C. Wang, Angela Krstic, Leonard Lee, Kwang-Ting Cheng, M. Ray Mercer, Thomas W. Williams, Magdy S. Abadir
2002	A	`conf`	A New ATPG Algorithm to Limit Test Set Size and Achieve Multiple Detections of All Faults. DATE Sooryong Lee, Brad Cobb, Jennifer Dworak, Michael R. Grimaila, M. Ray Mercer
2002	A	`conf`	Analysis of Delay Test Effectiveness with a Multiple-Clock Scheme. ITC Jing-Jia Liou, Li-C. Wang, Kwang-Ting Cheng, Jennifer Dworak, M. Ray Mercer, Rohit Kapur, Thomas W. Williams
2002	A	`conf`	Directed-Binary Search in Logic BIST Diagnostics. DATE Rohit Kapur, Thomas W. Williams, M. Ray Mercer
2002	A*	`conf`	Enhancing test efficiency for delay fault testing using multiple-clocked schemes. DAC Jing-Jia Liou, Li-C. Wang, Kwang-Ting Cheng, Jennifer Dworak, M. Ray Mercer, Rohit Kapur, Thomas W. Williams
2002	—	`conf`	Fortuitous Detection and its Impact on Test Set Sizes Using Stuck-at and Transition Faults. DFT Jennifer Dworak, James Wingfield, Brad Cobb, Sooryong Lee, Li-C. Wang, M. Ray Mercer
2001	J	`jnl`	Defect-Oriented Testing and Defective-Part-Level Prediction. IEEE Des. Test Comput. Jennifer Dworak, Jason D. Wicker, Sooryong Lee, Michael R. Grimaila, M. Ray Mercer, Kenneth M. Butler, Bret Stewart, Li-C. Wang
2000	A	`conf`	Enhanced DO-RE-ME based defect level prediction using defect site aggregation-MPG-D. ITC Jennifer Dworak, Michael R. Grimaila, Sooryong Lee, Li-C. Wang, M. Ray Mercer
2000	—	`conf`	On the superiority of DO-RE-ME/MPG-D over stuck-at-based defective part level prediction. Asian Test Symposium Jennifer Dworak, Michael R. Grimaila, Brad Cobb, Ting-Chi Wang, Li-C. Wang, M. Ray Mercer
1999	A	`conf`	Modeling the probability of defect excitation for a commercial IC with implications for stuck-at fault-based ATPG strategies. ITC Jennifer Dworak, Michael R. Grimaila, Sooryong Lee, Li-C. Wang, M. Ray Mercer
1999	C	`conf`	Multi-Level Logic Minimization through Fault Dictionary Analysis. ICCD Ronald W. Mehler, M. Ray Mercer
1999	Misc	`conf`	REDO - Probabilistic Excitation and Deterministic Observation - First Commercial Experimen. VTS Michael R. Grimaila, Sooryong Lee, Jennifer Dworak, Kenneth M. Butler, Bret Stewart, Hari Balachandran, Bryan Houchins, Vineet Mathur, Jaehong Park, Li-C. Wang, M. Ray Mercer
1996	C	`conf`	A Better ATPG Algorithm and Its Design Principles. ICCD Li-C. Wang, M. Ray Mercer, Thomas W. Williams
1996	J	`jnl`	Efficient logic-level timing analysis using constraint-guided critical path search. IEEE Trans. Very Large Scale Integr. Syst. Chanhee Oh, M. Ray Mercer
1996	A	`conf`	I ITC Thomas W. Williams, Robert H. Dennard, Rohit Kapur, M. Ray Mercer, Wojciech Maly
1996	—	`conf`	Iddq Testing for High Performance CMOS - The Next Ten Years. ED&TC Thomas W. Williams, Rohit Kapur, M. Ray Mercer, Robert H. Dennard, Wojciech Maly
1996	C	`conf`	Using Functional Information and Strategy Switching in Sequential ATPG. ICCD Jaehong Park, M. Ray Mercer
1996	A	`conf`	Using Target Faults To Detect Non-Tartget Defects. ITC Li-C. Wang, M. Ray Mercer, Thomas W. Williams
1995	—	`conf`	Enhanced testing performance via unbiased test sets. ED&TC Li-C. Wang, M. Ray Mercer, Thomas W. Williams
1995	—	`conf`	Improved sequential ATPG using functional observation information and new justification methods. ED&TC Jaehong Park, Chanhee Oh, M. Ray Mercer
1995	A	`conf`	On Efficiently and Reliably Achieving Low Defective Part Levels. ITC Li-C. Wang, M. Ray Mercer, Thomas W. Williams
1995	Misc	`conf`	On the decline of testing efficiency as fault coverage approaches 100%. VTS Li-C. Wang, M. Ray Mercer, Sophia W. Kao, Thomas W. Williams
1994	J	`jnl`	Least Upper Bounds an OBDD Sizes. IEEE Trans. Computers Mark A. Heap, M. Ray Mercer
1994	Misc	`conf`	Limitations in predicting defect level based on stuck-at fault coverage. VTS Jaehong Park, Mark Naivar, Rohit Kapur, M. Ray Mercer, Thomas W. Williams
1994	—	`conf`	Predicting Circuit Performance Using Circuit-level Statistical Timing Analysis. EDAC-ETC-EUROASIC Ronn B. Brashear, Noel Menezes, Chanhee Oh, Lawrence T. Pillage, M. Ray Mercer
1993	C	`conf`	An Efficient Symbolic Design Verification System. ICCD Jaehong Park, M. Ray Mercer
1993	Misc	`conf`	Combinational circuit ATPG using binary decision diagrams. VTS Sanjay Srinivasan, Gnanasekaran Swaminathan, James H. Aylor, M. Ray Mercer
1993	A	`conf`	Switch-Level ATPG Using Constraint-Guided Line Justification. ITC Eun Sei Park, M. Ray Mercer
1992	C	`conf`	A Synthesis Algorithm for Two-Level XOR Based Circuits. ICCD Mark A. Heap, William A. Rogers, M. Ray Mercer
1992	A	`conf`	All Tests for a Fault Are Not Equally Valuable for Defect Detection. ITC Rohit Kapur, Jaehong Park, M. Ray Mercer
1992	J	`jnl`	An efficient delay test generation system for combinational logic circuits. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Eun Sei Park, M. Ray Mercer
1992	J	`jnl`	Bounding Signal Probabilities for Testability Measurement Using Conditional Syndromes. IEEE Trans. Computers Rohit Kapur, M. Ray Mercer
1992	A	`conf`	ETA: electrical-level timing analysis. ICCAD Ronn B. Brashear, Douglas R. Holberg, M. Ray Mercer, Lawrence T. Pillage
1992	A*	`conf`	Functional Approaches to Generating Orderings for Efficient Symbolic Representations. DAC M. Ray Mercer, Rohit Kapur, Don E. Ross
1992	J	`jnl`	The Total Delay Fault Model and Statistical Delay Fault Coverage. IEEE Trans. Computers Eun Sei Park, M. Ray Mercer, Thomas W. Williams
1992	Misc	`conf`	The roles of controllability and observability in design for test. VTS Kenneth M. Butler, Rohit Kapur, M. Ray Mercer, Don E. Ross
1991	A	`conf`	Delay Testing Quality in Timing-Optimized Designs. ITC Eun Sei Park, Bill Underwood, Thomas W. Williams, M. Ray Mercer
1991	J	`jnl`	Exact ordered binary decision diagram size when representing classes of symmetric functions. J. Electron. Test. Don E. Ross, Kenneth M. Butler, M. Ray Mercer
1991	—	`conf`	Fast functional evaluation of candidate OBDD variable orderings. EURO-DAC Don E. Ross, Kenneth M. Butler, Rohit Kapur, M. Ray Mercer
1991	A*	`conf`	Heuristics to Compute Variable Orderings for Efficient Manipulation of Ordered Binary Decision Diagrams. DAC Kenneth M. Butler, Don E. Ross, Rohit Kapur, M. Ray Mercer
1991	J	`jnl`	Testing and Design Verification of Electronic Components. Computer M. Ray Mercer
1991	A*	`conf`	The Interdependence Between Delay-Optimization of Synthesized Networks and Testing. DAC Thomas W. Williams, Bill Underwood, M. Ray Mercer
1990	A*	`conf`	An Efficient Delay Test Generation System for Combinational Logic Circuits. DAC Eun Sei Park, M. Ray Mercer
1990	J	`jnl`	Guest Editorial: ITC 20th Anniversary. IEEE Des. Test Comput. M. Ray Mercer
1990	A*	`conf`	The Influences of Fault Type and Topology on Fault Model Performance and the Implications to Test and Testable Design. DAC Kenneth M. Butler, M. Ray Mercer
1989	A*	`conf`	A Deterministic Approach to Adjacency Testing for Delay Faults. DAC C. Thomas Glover, M. Ray Mercer
1989	J	`jnl`	A statistical model for delay-fault testing. IEEE Des. Test Eun Sei Park, M. Ray Mercer, Thomas W. Williams
1988	A*	`conf`	A Method of Delay Fault Test Generation. DAC C. Thomas Glover, M. Ray Mercer
1988	J	`jnl`	Algorithms for automatic test pattern generation. IEEE Des. Test Tom E. Kirkland, M. Ray Mercer
1988	A*	`conf`	CATAPULT: Concurrent Automatic Testing Allowing Parallelization and Using Limited Topology. DAC Rhonda Kay Gaede, Don E. Ross, M. Ray Mercer, Kenneth M. Butler
1988	A	`conf`	D^3FS: A Demand Driven Deductive Fault Simulator. ITC Steven P. Smith, Bill Underwood, M. Ray Mercer
1988	A	`conf`	Statistical Delay Fault Coverage and Defect Level for Delay Faults. ITC Eun Sei Park, Thomas W. Williams, M. Ray Mercer
1987	A*	`conf`	A Topological Search Algorithm for ATPG. DAC Tom E. Kirkland, M. Ray Mercer
1987	A*	`conf`	Demand Driven Simulation: BACKSIM. DAC Steven P. Smith, M. Ray Mercer, B. Brodk
1986	—	`conf`	A Two-Level Guidance Heuristic for ATPG. FJCC Tom E. Kirkland, M. Ray Mercer
1986	A	`conf`	Calculation of Greatest Lower Bounds Obtainable by the Cutting Algorithm. ITC Rhonda Kay Gaede, M. Ray Mercer, Bill Underwood
1986	J	`jnl`	Derivation and Refinement of Fan-Out Constraints to Generate Tests in Combinational Logic Circuits. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Ki Soo Hwang, M. Ray Mercer
1986	A	`conf`	Deterministic Versus Random Testing. ITC Vishwani D. Agrawal, M. Ray Mercer
1986	A	`conf`	Informed Test Generation Guidance Using Partially Specified Fanout Constraints. ITC Ki Soo Hwang, M. Ray Mercer
1986	A	`conf`	Logic Elements for Universally Testable Circuits. ITC M. Ray Mercer
1985	A	`conf`	Built-In Self Test Input Generator for Programmable Logic Arrays. ITC John Salick, Bill Underwood, M. Ray Mercer
1985	A*	`conf`	CADTOOLS: a CAD algorithm development system. DAC Eric Schell, M. Ray Mercer
1984	A	`conf`	Correlating Testability with Fault Detection. ITC Bill Underwood, M. Ray Mercer
1983	A	`conf`	Testing Issues at the University of Texas. ITC M. Ray Mercer
1982	A	`conf`	Testability Measures : What Do They Tell Us ? ITC Vishwani D. Agrawal, M. Ray Mercer
1981	A	`conf`	Test Generation for Highly Sequential Scan-Testable Circuits Through Logic Transformation. ITC M. Ray Mercer, Vishwani D. Agrawal, Carlos M. Roman