M. H. Vasantha

48 papers C 6Misc 3Journal 15Unranked 24
YearRankTypeTitle / Venue / Authors
2026 J jnl
MFDFA-Enhanced GAN: A Hardware-Optimized Architecture for Efficient Synthetic Image Generation.
IEEE Access
Charudatta Korde, K. G. Shreeharsha, Siddharth R. K., M. H. Vasantha, Y. B. Nithin Kumar
2025 J jnl
Evolutionary-Enhanced GAN With Wavelet-Based Discrimination: A Hardware-Accelerated Architecture for Efficient Synthetic Image Generation.
IEEE Access
Charudatta Korde, K. G. Shreeharsha, Siddharth R. K., M. H. Vasantha, Y. B. Nithin Kumar
2025 J jnl
Generating Synthetic Data Using 2D Multifractal Detrended Fluctuation Analysis Generative Adversarial Networks.
IEEE Access
Charudatta Korde, K. G. Shreeharsha, Siddharth R. K., M. H. Vasantha, Y. B. Nithin Kumar
2024 J jnl
An Error Bound Particle Swarm Optimization for Analog Circuit Sizing.
IEEE Access
K. G. Shreeharsha, Siddharth R. K., M. H. Vasantha, Kumar Y. B. Nithin
2024 J jnl
N-Parallel Paths-Based D-Latch for High-Speed Applications.
IEEE Access
Rakhi R., Siddharth R. K., K. G. Shreeharsha, M. H. Vasantha, Nithin Kumar Yernad Balachandra
2023 C conf
A 11-ns, 3.85-fJ, Deep Sub-threshold, Energy Efficient Level Shifter in 65-nm CMOS.
ISCAS
R. D. Balaji, Siddharth R. K., Sanmitra Bharat Naik, Y. B. Nithin Kumar, M. H. Vasantha, Edoardo Bonizzoni
2023 J jnl
Partition Bound Random Number-Based Particle Swarm Optimization for Analog Circuit Sizing.
IEEE Access
K. G. Shreeharsha, Siddharth R. K., M. H. Vasantha, Y. B. Nithin Kumar
2022 C conf
On The Design Of Rationalised Bi-orthogonal Wavelet Using Reversible Logic.
ISCAS
Sithara Raveendran, Pranose J. Edavoor, Y. B. Nithin Kumar, M. H. Vasantha
2021 J jnl
$\pm \, 0.5$ V, 254 $\upmu $W Second-Order Tunable Biquad Low-Pass Filter with 7.3 fJ FOM Using a Novel Low-Voltage Fully Balanced Current-Mode Circuit.
Circuits Syst. Signal Process.
P. S. Veerendranath, Vivek Sharma, M. H. Vasantha, Y. B. Nithin Kumar
2021 Misc conf
A 1 V Double-Balanced Mixer for 2.4-2.5 GHz ISM Band Applications.
VLSID
Sanmitra Bharat Naik, Siddharth R. K., Anirban Chatterjee, Kumar Y. B. Nithin, M. H. Vasantha, Ramnath Kini
2021 — conf
A 1-V, 10-bit, 250 MS/s, Current-Steering Segmented DAC for Video Applications.
ISVLSI
Shiv Chandra Kumar, Siddharth R. K., Nithin Kumar Y. B., M. H. Vasantha
2021 J jnl
A Novel Complex Filter Design With Dual Feedback for High Frequency Wireless Receiver Applications.
IEEE Trans. Circuits Syst. II Express Briefs
P. S. Veerendranath, Vivek Sharma, M. H. Vasantha, Y. B. Nithin Kumar
2021 J jnl
Inexact Signed Wallace Tree Multiplier Design Using Reversible Logic.
IEEE Access
Sithara Raveendran, Pranose J. Edavoor, Nithin Kumar Yernad Balachandra, M. H. Vasantha
2021 J jnl
Quantization aware approximate multiplier and hardware accelerator for edge computing of deep learning applications.
Integr.
Karri Manikantta Reddy, M. H. Vasantha, Nithin Y. B. Kumar, Ch. Keshava Gopal, Devesh Dwivedi
2021 — conf
Training of Generative Adversarial Networks using Particle Swarm Optimization Algorithm.
iSES
K. G. Shreeharsha, Charudatta Korde, M. H. Vasantha, Y. B. Nithin Kumar
2020 — conf
A 1 V, 39 μ W, 5-bit Multi-Level Comparator based Flash ADC.
iSES
Nitish Kumar, Siddharth R. K., Nithin Y. B. Kumar, M. H. Vasantha
2020 J jnl
A 1-V, 3-GHz Strong-Arm Latch Voltage Comparator for High Speed Applications.
IEEE Trans. Circuits Syst.
Siddharth R. K., Y. Jaya Satyanarayana, Nithin Y. B. Kumar, M. H. Vasantha, Edoardo Bonizzoni
2020 — conf
A 1.8 V Quadrature Phase LC Oscillator for 5G Applications.
iSES
Sanmitra Bharat Naik, Siddharth R. K., Anirban Chatterjee, Nithin Kumar Y. B., M. H. Vasantha, Ramnath Kini
2020 J jnl
An Approximate Low-Power Lifting Scheme Using Reversible Logic.
IEEE Access
Sithara Raveendran, Pranose J. Edavoor, Nithin Y. B. Kumar, M. H. Vasantha
2020 J jnl
Approximate radix-8 Booth multiplier for low power and high speed applications.
Microelectron. J.
Bipul Boro, Karri Manikantta Reddy, Nithin Y. B. Kumar, M. H. Vasantha
2020 J jnl
Design of Approximate Booth Squarer for Error-Tolerant Computing.
IEEE Trans. Very Large Scale Integr. Syst.
Karri Manikantta Reddy, M. H. Vasantha, Nithin Y. B. Kumar, Devesh Dwivedi
2020 J jnl
Power Saving Scheme for Process Corner Calibrated Standard Cell Based Flash ADC in Wireless Surveillance Applications.
SN Comput. Sci.
Siddharth R. K., Nithin Y. B. Kumar, M. H. Vasantha
2020 — conf
Reversible Logic Implementation of Image Denoising for Grayscale Images.
MWSCAS
Sithara Raveendran, Pranose J. Edavoor, Nithin Kumar Y. B., M. H. Vasantha
2019 — conf
An Asynchronous Analog to Digital Converter for Video Camera Applications.
ISVLSI
Sunil R., Siddharth R. K., Nithin Y. B. Kumar, M. H. Vasantha
2019 C conf
Current Conveyor based Novel Gyrator filter for Biomedical Sensor Applications.
TENCON
P. S. Veerendranath, Vivek Sharma, Nithin Y. B. Kumar, M. H. Vasantha, Edoardo Bonizzoni
2019 — conf
Two-Step Flash ADC Using Standard Cell Based Flash ADCs.
iSES
Rahul E., Siddharth R. K., Vivek Sharma, M. H. Vasantha, Nithin Kumar Yernad Balachandra
2018 — conf
A 0.5 V Low Power DTMOS OTA-C Filter for ECG Sensing Applications.
IEEE SENSORS
Purnima Kalekar, Prasad Vernekar, M. H. Vasantha, Y. B. Nithin Kumar, Edoardo Bonizzoni
2018 C conf
A Low-Power Auxiliary Circuit for Level-Crossing ADCs in IoT-Sensor Applications.
ISCAS
Siddharth R. K., Kumar Y. B. Nithin, M. H. Vasantha, Edoardo Bonizzoni
2018 Misc conf
A Novel Low Power G m-C Continuous-Time Analog Filter with Wide Tuning Range.
VLSID
P. S. Veerendranath, M. H. Vasantha, Kumar Y. B. Nithin, Edoardo Bonizzoni
2018 — conf
An Asynchronous Analog to Digital Converter for Surveillance Camera Applications.
ISVLSI
Siddharth R. K., Sunil R., Nithin Y. B. Kumar, M. H. Vasantha, Edoardo Bonizzoni
2018 C conf
Characterization of a Novel Low Leakage Power-Efficient Asymmetric 7T SRAM Cell.
TENCON
Dhavala Shashidhar, Vivek Sharma, Gurusiddappa R. Prashanth, Nithin Y. B. Kumar, M. H. Vasantha
2018 — conf
Design and Analysis of Approximate Multipliers for Error-Tolerant Applications.
iSES
Anirudha Pandey, Karri Manikantta Reddy, Praveen Yadav, Nithin Y. B. Kumar, M. H. Vasantha
2018 C conf
Design and Implementation of Reversible Logic based RGB to Gray scale Color Space Converter.
TENCON
Sithara Raveendran, Pranose J. Edavoor, Nithin Y. B. Kumar, M. H. Vasantha
2018 — conf
Design of Approximate Dividers for Error Tolerant Applications.
MWSCAS
Karri Manikantta Reddy, M. H. Vasantha, Kumar Y. B. Nithin, Devesh Dwivedi
2018 — conf
Design of Area-Power-Delay Efficient Square Root Carry Select Adder.
iSES
Chetan Kamble, Siddharth R. K., Shivnarayan Patidar, M. H. Vasantha, Nithin Y. B. Kumar
2018 — conf
FPGA Implementation of Square and Cube Architecture Using Vedic Mathematics.
iSES
Sampada Barve, Sithara Raveendran, Charudatta Korde, Trilochan Panigrahi, Nithin Y. B. Kumar, M. H. Vasantha
2018 — conf
Low Power Approximate Multipliers With Truncated Carry Propagation for LSBs.
MWSCAS
Praveen Yadav, Anirudha Pandey, Karri Manikantta Reddy, K. J. Ravi Prasad, M. H. Vasantha, Nithin Y. B. Kumar
2018 — conf
Performance Enhancement of Split Length Compensated Operational Amplifiers.
ISVLSI
Donel Anto, Abhijeet D. Taralkar, Kumar Y. B. Nithin, M. H. Vasantha
2017 — conf
A 0.5 V Low Power OTA-C Low Pass Filter for ECG Detection.
ISVLSI
Rakhi R., Abhijeet D. Taralkar, M. H. Vasantha, Kumar Y. B. Nithin
2017 — conf
Design of 5-Bit Flash ADC Using Multiple Input Standard Cell Gates for Large Input Swing.
ISVLSI
Sumit Khalapure, Siddharth R. K., Kumar Y. B. Nithin, M. H. Vasantha
2017 — conf
Design of Low Power 4-Bit 400MS/s Standard Cell Based Flash ADC.
ISVLSI
S. M. Mayur, Siddharth R. K., Kumar Y. B. Nithin, M. H. Vasantha
2016 — conf
A Gracefully Degrading and Energy-Efficient Fault Tolerant NoC Using Spare Core.
ISVLSI
B. Naresh Kumar Reddy, M. H. Vasantha, Kumar Y. B. Nithin
2016 Misc conf
Characterization of a Novel Low Leakage Power and Area Efficient 7T SRAM Cell.
VLSID
A. Venkatareddy, Sithara Raveendran, Kumar Y. B. Nithin, M. H. Vasantha
2016 — conf
Design and Analysis of Novel InSb/Si Heterojunction Double Gate Tunnel Field Effect Transistor.
ISVLSI
S. Ahish, Dheeraj Sharma, M. H. Vasantha, Kumar Y. B. Nithin
2016 — conf
Design and Implementation of Tunable Bandpass Filter for Biomedical Applications.
iNIS
Saurabh B. Kaurati, Nithin Y. B. Kumar, Shivnarayan Patidar, M. H. Vasantha
2016 — conf
Design of Low Power 5-Bit Hybrid Flash ADC.
ISVLSI
S. M. Mayur, Siddharth R. K., Kumar Y. B. Nithin, M. H. Vasantha
2016 — conf
FPGA realisation of PSNR and BPP driven Adaptive Compression and Encryption Algorithm for RGB Images.
ICCCNT
Pranose J. Edavoor, Sithara Raveendran, Arjun T. V., Sumesh K. P., Kumar Y. B. Nithin, M. H. Vasantha
2015 — conf
Low power, high speed error tolerant multiplier using approximate adders.
VDAT
Karri Manikantta Reddy, Kumar Y. B. Nithin, Dheeraj Sharma, M. H. Vasantha