M. Balakrishnan

125 papers A* 4A 10B 5C 7Misc 35Journal 33Unranked 31
YearRankTypeTitle / Venue / Authors
2025 J jnl
EXPRESS: A Framework for Execution Time Prediction of Concurrent CNNs on Xilinx DPU Accelerator.
ACM Trans. Embed. Comput. Syst.
Shikha Goel, Rajesh Kedia, Rijurekha Sen, M. Balakrishnan
2022 C conf
Beacon Placement and Signal Strength Estimation to Improve Localization Coverage and Accuracy.
IPIN
Vikas Upadhyay, Kashi Roy, M. Balakrishnan
2022 J jnl
Computing and assistive technology solutions for the visually impaired.
Commun. ACM
M. Balakrishnan
2022 — conf
EXPRESS: CNN EXecution Time PREdiction for DPU DeSign Space Exploration.
FPT
Shikha Goel, Rajesh Kedia, Rijurekha Sen, M. Balakrishnan
2021 — conf
ASSISTECH: An Accidental Journey into Assistive Technology.
A Journey of Embedded and Cyber-Physical Systems
M. Balakrishnan
2021 J jnl
Design Space Exploration of FPGA-Based System With Multiple DNN Accelerators.
IEEE Embed. Syst. Lett.
Rajesh Kedia, Shikha Goel, M. Balakrishnan, Kolin Paul, Rijurekha Sen
2021 B conf
EnergyNN: Energy Estimation for Neural Network Inference Tasks on DPU.
FPL
Shikha Goel, M. Balakrishnan, Rijurekha Sen
2021 J jnl
Performance-Energy Trade-off in Modern CMPs.
ACM Trans. Archit. Code Optim.
Solomon Abera, M. Balakrishnan, Anshul Kumar
2021 A* conf
VmAP: A Fair Metric for Video Object Detection.
ACM Multimedia
Anupam Sobti, Vaibhav Mavi, M. Balakrishnan, Chetan Arora
2020 — conf
A Genetic Algorithm Based Medical Image Watermarking for Improving Robustness and Fidelity in Wavelet Domain.
FICTA (2)
Balasamy Krishnasamy, M. Balakrishnan, Arockia Christopher
2020 — conf
INFER: INterFerence-aware Estimation of Runtime for Concurrent CNN Execution on DPUs.
FPT
Shikha Goel, Rajesh Kedia, M. Balakrishnan, Rijurekha Sen
2019 Misc conf
A case for design space exploration of context-aware adaptive embedded systems: work-in-progress.
CODES+ISSS
Rajesh Kedia, M. Balakrishnan, Kolin Paul
2019 J jnl
Equivalence Checking and Compaction of n-input Majority Terms Using Implicants of Majority.
J. Electron. Test.
Rajeswari Devadoss, Kolin Paul, M. Balakrishnan
2019 — conf
Evaluating the Use of Variable Height in Tactile Graphics.
WHC
Richa Gupta, P. V. M. Rao, M. Balakrishnan, S. Mannheimer
2019 C conf
GRanDE: Graphical Representation and Design Space Exploration of Embedded Systems.
DSD
Rajesh Kedia, M. Balakrishnan, Kolin Paul
2019 Misc conf
MAVI: Mobility Assistant for Visually Impaired with Optional Use of Local and Cloud Resources.
VLSID
Rajesh Kedia, Anupam Sobti, Mukund Rungta, Sarvesh Chandoliya, Akhil Soni, Anil Kumar Meena, Chrystle Myrna Lobo, Richa Verma, M. Balakrishnan, Chetan Arora
2019 — conf
ML Guided Energy-Performance Trade-Off Estimation For Uncore Frequency Scaling.
SpringSim
Solomon Abera Bekele, M. Balakrishnan, Anshul Kumar
2019 Misc conf
Majority Logic: Prime Implicants and n-Input Majority Term Equivalence.
VLSID
Rajeswari Devadoss, Kolin Paul, M. Balakrishnan
2019 C conf
Multi-sensor Energy Efficient Obstacle Detection.
DSD
Anupam Sobti, M. Balakrishnan, Chetan Arora
2018 — conf
FPGA-Based Controllers for Compact Low Power Refreshable Braille Display.
ISVLSI
Suman Adhepalli Muralikrishnan, Pulkit Sapra, Saurabh Agrawal, Piyush Chanana, M. Balakrishnan, P. V. M. Rao
2018 A conf
Object Detection in Real-Time Systems: Going Beyond Precision.
WACV
Anupam Sobti, Chetan Arora, M. Balakrishnan
2018 — conf
Performance-Energy Trade-off in CMPs with Per-Core DVFS.
ARCS
Solomon Abera, M. Balakrishnan, Anshul Kumar
2018 J jnl
Task Assignment Algorithms for Multicore Platforms with Process Variations.
J. Low Power Electron.
Gayathri Ananthanarayanan, Smruti R. Sarangi, M. Balakrishnan
2017 J jnl
Hardware acceleration of de novo genome assembly.
Int. J. Embed. Syst.
B. Sharat Chandra Varma, Kolin Paul, M. Balakrishnan, Dominique Lavenier
2017 Misc conf
MAVI: An Embedded Device to Assist Mobility of Visually Impaired.
VLSID
Rajesh Kedia, K. K. Yoosuf, Pappireddy Dedeepya, Munib Fazal, Chetan Arora, M. Balakrishnan
2017 J jnl
Optimal mapping of program overlays onto many-core platforms with limited memory capacity.
Des. Autom. Embed. Syst.
Mansureh Shahraki Moghaddam, M. Balakrishnan, Kiyoung Choi
2017 — conf
PLSS: A Scheduler for Multi-core Embedded Systems.
ARCS
Solomon Abera, M. Balakrishnan, Anshul Kumar
2016 — conf
Leakage Power Aware Task Assignment Algorithms for Multicore Platforms.
ISVLSI
Gayathri Ananthanarayanan, Smruti R. Sarangi, M. Balakrishnan
2015 J jnl
Configurable Architectures for Multi-Mode Floating Point Adders.
IEEE Trans. Circuits Syst. I Regul. Pap.
Manish Kumar Jaiswal, B. Sharat Chandra Varma, Hayden Kwok-Hay So, M. Balakrishnan, Kolin Paul, Ray C. C. Cheung
2015 J jnl
E-Super Vertex In-Magic Total Labelings of Digraphs.
Electron. Notes Discret. Math.
S. Arumugam, M. Balakrishnan, G. Marimuthu
2015 J jnl
Improving Map-Reduce for GPUs with cache.
Int. J. High Perform. Syst. Archit.
Arun Parakh, M. Balakrishnan, Kolin Paul
2015 — conf
Partial Reconfiguration for Dynamic Mapping of Task Graphs onto 2D Mesh Platform.
ARC
Mansureh Shahraki Moghaddam, M. Balakrishnan, Kolin Paul
2015 J jnl
Super Edge Magic Graceful Labeling of Generalized Petersen Graphs.
Electron. Notes Discret. Math.
G. Marimuthu, S. Kavitha, M. Balakrishnan
2015 J jnl
Vertex in-magic arc labelings of digraphs.
Electron. Notes Discret. Math.
M. Balakrishnan, G. Marimuthu, S. Arumugam
2014 Misc conf
Accelerating Genome Assembly Using Hard Embedded Blocks in FPGAs.
VLSID
B. Sharat Chandra Varma, Kolin Paul, M. Balakrishnan
2014 — conf
Configurable Architecture for Double/Two-Parallel Single Precision Floating Point Division.
ISVLSI
Manish Kumar Jaiswal, Ray C. C. Cheung, M. Balakrishnan, Kolin Paul
2014 — conf
Edutactile - A Tool for Rapid Generation of Accurate Guideline-Compliant Tactile Graphics for Science and Mathematics.
ICCHP (2)
Mrinal Mech, Kunal Kwatra, Supriya Das, Piyush Chanana, Rohan Paul, M. Balakrishnan
2014 C conf
High Level Design Approach to Accelerate De Novo Genome Assembly Using FPGAs.
DSD
B. Sharat Chandra Varma, Kolin Paul, M. Balakrishnan
2014 — conf
LightSim: A leakage aware ultrafast temperature simulator.
ASP-DAC
Smruti R. Sarangi, Gayathri Ananthanarayanan, M. Balakrishnan
2014 Misc conf
Mapping Tasks to a Dynamically Reconfigurable Coarse Grained Array.
FCCM
Mansureh Shahraki Moghaddam, Kolin Paul, M. Balakrishnan
2014 J jnl
Series Expansion based Efficient Architectures for Double Precision Floating Point Division.
Circuits Syst. Signal Process.
Manish Kumar Jaiswal, Ray C. C. Cheung, M. Balakrishnan, Kolin Paul
2014 J jnl
Super edge magic graceful graphs.
Inf. Sci.
G. Marimuthu, M. Balakrishnan
2014 J jnl
Unified Architecture for Double/Two-Parallel Single Precision Floating Point Adder.
IEEE Trans. Circuits Syst. II Express Briefs
Manish Kumar Jaiswal, Ray C. C. Cheung, M. Balakrishnan, Kolin Paul
2013 A conf
A path-guided audio based indoor navigation system for persons with visual impairment.
ASSETS
Dhruv Jain, Akhil Jain, Rohan Paul, Akhila Komarika, M. Balakrishnan
2013 Misc conf
Accelerating 3D-FFT Using Hard Embedded Blocks in FPGAs.
VLSI Design
B. Sharat Chandra Varma, Kolin Paul, M. Balakrishnan
2013 J jnl
Amdahl's law in the era of process variation.
Int. J. High Perform. Syst. Archit.
Gayathri Ananthanarayanan, Geetika Malhotra, M. Balakrishnan, Smruti R. Sarangi
2013 — conf
Design and Implementation of High Performance Architectures with Partially Reconfigurable CGRAs.
IPDPS Workshops
Mansureh Shahraki Moghaddam, Kolin Paul, M. Balakrishnan
2013 Misc conf
FAssem: FPGA Based Acceleration of De Novo Genome Assembly.
FCCM
B. Sharat Chandra Varma, Kolin Paul, M. Balakrishnan, Dominique Lavenier
2012 J jnl
E-super vertex magic labelings of graphs.
Discret. Appl. Math.
G. Marimuthu, M. Balakrishnan
2012 J jnl
Measures and Countermeasures for Null Frequency Jamming of On-Demand Routing Protocols in Wireless Ad Hoc Networks.
IEEE Trans. Wirel. Commun.
M. Balakrishnan, Hong Huang, Rafael Asorey-Cacheda, Satyajayant Misra, Sandeep Pawar, Yousef Jaradat
2012 — conf
Performance Estimation of GPUs with Cache.
IPDPS Workshops
Arun Parakh, M. Balakrishnan, Kolin Paul
2012 — conf
Power Consumption in Multi-core Processors.
IC3
M. Balakrishnan
2012 J jnl
System-Level Design Space Exploration Methodology for Energy-Efficient Sensor Node Configurations: An Experimental Validation.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Sonali Chouhan, M. Balakrishnan, Ranjan Bose
2011 — conf
Architecture and tools for programmable QCA.
FPT
Rajeswari Devadoss, Kolin Paul, M. Balakrishnan
2011 J jnl
Compressing Cache State for Postsilicon Processor Debug.
IEEE Trans. Computers
Preeti Ranjan Panda, M. Balakrishnan, Anant Vishnoi
2011 J jnl
p-QCA: A Tiled Programmable Fabric Architecture Using Molecular Quantum-Dot Cellular Automata.
ACM J. Emerg. Technol. Comput. Syst.
Rajeswari Devadoss, Kolin Paul, M. Balakrishnan
2010 — conf
A tiled programmable fabric using QCA.
FPT
Rajeswari Devadoss, Kolin Paul, M. Balakrishnan
2010 Misc conf
Clocking-Based Coplanar Wire Crossing Scheme for QCA.
VLSI Design
Rajeswari Devadoss, Kolin Paul, M. Balakrishnan
2010 C conf
Enhancing post-silicon processor debug with Incremental Cache state Dumping.
VLSI-SoC
Preeti Ranjan Panda, Anant Vishnoi, M. Balakrishnan
2009 J jnl
A Framework for Energy-Consumption-Based Design Space Exploration for Wireless Sensor Nodes.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Sonali Chouhan, Ranjan Bose, M. Balakrishnan
2009 A conf
A generic platform for estimation of multi-threaded program performance on heterogeneous multiprocessors.
DATE
Aryabartta Sahu, M. Balakrishnan, Preeti Ranjan Panda
2009 A conf
An experimental validation of system level design space exploration methodology for energy efficient sensor nodes.
ISLPED
Sonali Chouhan, M. Balakrishnan, Ranjan Bose
2009 A conf
Cache aware compression for processor debug support.
DATE
Anant Vishnoi, Preeti Ranjan Panda, M. Balakrishnan
2009 J jnl
Integrated energy analysis of error correcting codes and modulation for energy efficient wireless sensor nodes.
IEEE Trans. Wirel. Commun.
Sonali Chouhan, Ranjan Bose, M. Balakrishnan
2009 A* conf
Online cache state dumping for processor debug.
DAC
Anant Vishnoi, Preeti Ranjan Panda, M. Balakrishnan
2008 A conf
A framework for energy consumption based design space exploration for wireless sensor nodes.
ISLPED
Sonali Chouhan, M. Balakrishnan, Ranjan Bose
2007 B conf
A Behavioral Synthesis Approach for Distributed Memory FPGA Architectures.
FPL
Ashutosh Pal, M. Balakrishnan
2007 J jnl
Evaluation of Bus Based Interconnect Mechanisms in Clustered VLIW Architectures.
Int. J. Parallel Program.
Anup Gangwar, M. Balakrishnan, Preeti Ranjan Panda, Anshul Kumar
2007 J jnl
Impact of intercluster communication mechanisms on ILP in clustered VLIW architectures.
ACM Trans. Design Autom. Electr. Syst.
Anup Gangwar, M. Balakrishnan, Anshul Kumar
2007 — conf
Yield Prediction Through Feed Forward Neural Network Approach for Direct Seeded Rice (Oryza sativa) in Bay Islands.
IICAI
M. Balakrishnan, N. Ravisankar, K. Meena, R. Elanchezhian, S. K. Zamir Ahmed
2006 Misc conf
New approach to architectural synthesis: incorporating QoS constraint.
EMSOFT
Harsh Dhand, Basant Kumar Dwivedi, M. Balakrishnan
2006 C conf
Rapid Resource-Constrained Hardware Performance Estimation.
IEEE International Workshop on Rapid System Prototyping
Basant Kumar Dwivedi, Arun Kejariwal, M. Balakrishnan, Anshul Kumar
2006 Misc conf
Sequential Equivalence Checking.
VLSI Design
Anmol Mathur, Masahiro Fujita, M. Balakrishnan, Raj S. Mitra
2005 — conf
A Specialized Graduate Program in VLSI Design Tools and Technology.
MSE
M. Balakrishnan, B. S. Panwar
2005 Misc conf
ADOPT: An Approach to Activity Based Delay Optimization.
VLSI Design
Gaurav Arora, Abhishek Sharma, D. Nagchoudhuri, M. Balakrishnan
2005 A conf
Evaluation of Bus Based Interconnect Mechanisms in Clustered VLIW Architectures.
DATE
Anup Gangwar, M. Balakrishnan, Preeti Ranjan Panda, Anshul Kumar
2005 Misc conf
Integrated On-Chip Storage Evaluation in ASIP Synthesis.
VLSI Design
Manoj Kumar Jain, M. Balakrishnan, Anshul Kumar
2005 A conf
SMPS: an FPGA-based prototyping environment for multiprocessor embedded systems (abstract only).
FPGA
Ankit Mathur, Mayank Agarwal, Soumyadeb Mitra, Anup Gangwar, M. Balakrishnan, Subhashis Banerjee
2004 J jnl
An efficient technique for exploring register file size in ASIP design.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Manoj Kumar Jain, M. Balakrishnan, Anshul Kumar
2004 Misc conf
Automatic synthesis of system on chip multiprocessor architectures for process networks.
CODES+ISSS
Basant Kumar Dwivedi, Anshul Kumar, M. Balakrishnan
2004 Misc conf
Synthesis of Application Specific Multiprocessor Architectures for Process Networks.
VLSI Design
Basant Kumar Dwivedi, Anshul Kumar, M. Balakrishnan
2003 C conf
Exploring Storage Organization in ASIP Synthesis.
DSD
Manoj Kumar Jain, M. Balakrishnan, Anshul Kumar
2003 Misc conf
SoC Synthesis with Automatic Hardware Software Interface Generation.
VLSI Design
Amarjeet Singh, Amit Chhabra, Anup Gangwar, Basant Kumar Dwivedi, M. Balakrishnan, Anshul Kumar
2002 — conf
A New Divide and Conquer Method for Achieving High Speed Division in Hardware.
ASP-DAC/VLSI Design
Murali Mohan, Rohini Krishnan, Anshul Kumar, M. Balakrishnan
2002 — conf
A New Performance Evaluation Approach for System Level Design Space Exploration.
ISSS
M. Balakrishnan, Anshul Kumar, C. P. Joshi
2002 — conf
A Trimaran Based Framework for Exploring the Design Space of VLIW ASIPs with Coarse Grain Functional Units.
ISSS
M. Balakrishnan, Anshul Kumar, Paolo Ienne, Anup Gangwar, Bhuvan Middha
2002 Misc conf
An efficient technique for exploring register file size in ASIP synthesis.
CASES
Manoj Kumar Jain, M. Balakrishnan, Anshul Kumar
2002 — conf
Exploring the Number of Register Windows in ASIP Synthesis.
ASP-DAC/VLSI Design
Vishal P. Bhatt, M. Balakrishnan, Anshul Kumar
2002 — conf
Reducing Energy Consumption by Dynamic Copying of Instructions onto Onchip Memory.
ISSS
M. Balakrishnan, Peter Marwedel, Lars Wehmeyer, Nils Grunwald, Rajeshwari Banakar, Stefan Steinke
2002 — conf
Scratchpad memory: design alternative for cache on-chip memory in embedded systems.
CODES
Rajeshwari Banakar, Stefan Steinke, Bo-Sik Lee, M. Balakrishnan, Peter Marwedel
2001 — conf
A Specialized Graduate Program in VLSI Design: A Success Story.
MSE
M. Balakrishnan
2001 Misc conf
ASIP Design Methodologies : Survey and Issues.
VLSI Design
Manoj Kumar Jain, M. Balakrishnan, Anshul Kumar
2001 J jnl
Analysis of the influence of register file size on energyconsumption, code size, and execution time.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Lars Wehmeyer, Manoj Kumar Jain, Stefan Steinke, Peter Marwedel, M. Balakrishnan
2001 — conf
Evaluating register file size in ASIP design.
CODES
Manoj Kumar Jain, Lars Wehmeyer, Stefan Steinke, Peter Marwedel, M. Balakrishnan
2001 — conf
Exploring design space of parallel realizations: MPEG-2 decoder case study.
CODES
Basant Kumar Dwivedi, Jan Hoogerbrugge, Paul Stravers, M. Balakrishnan
2001 Misc conf
Integrating Communication Cost Estimation in Embedded Systems Design : A PCI Case Study.
VLSI Design
Anupam Rastogi, M. Balakrishnan, Anshul Kumar
2000 J jnl
Allocation of FIFO structures in RTL data paths.
ACM Trans. Design Autom. Electr. Syst.
M. Balakrishnan, Heman Khanna
2000 Misc conf
Optimal Hardware/Software Partitioning for Concurrent Specification Using Dynamic Programming.
VLSI Design
Aviral Shrivastava, Mohit Kumar, Sanjiv Kapoor, Shashi Kumar, M. Balakrishnan
2000 Misc conf
Processor Evaluation in an Embedded Systems Design Environment.
VLSI Design
T. Vinod Kumar Gupta, Purvesh Sharma, M. Balakrishnan, Sharad Malik
2000 A conf
Speeding up power estimation of embedded software.
ISLPED
Akshaye Sama, J. F. M. Theeuwen, M. Balakrishnan
2000 Misc conf
nterface Synthesis: Issues and Approaches.
VLSI Design
Arvind Rajawat, M. Balakrishnan, Anshul Kumar
1999 A conf
Hardware/Software Partitioning Between Microprocessor and Reconfigurable Hardware.
FPGA
M. Anand, Sanjiv Kapoor, M. Balakrishnan
1999 Misc conf
MPEG-2 Video Data Simulator: A Case Study in Constrained HW-SW Codesign.
VLSI Design
Rashmi Goswami, V. Srinivasan, M. Balakrishnan
1999 Misc conf
Simulation and Modeling of a Multicast ATM Switch.
VLSI Design
Ajoy C. Siddabathuni, M. Balakrishnan
1998 J jnl
Direct mapping of RTL structures onto LUT-based FPGA's.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
A. R. Naseer, M. Balakrishnan, Anshul Kumar
1998 Misc conf
Real Time Collision Detection and Avoidance: A Case Study for Design Space Exploration in HW-SW Codesign.
VLSI Design
Sandeep K. Lodha, Shashank Gupta, M. Balakrishnan, Subhashis Banerjee
1998 Misc conf
Speeding Up Program Execution Using Reconfigurable Hardware and a Hardware Function Library.
VLSI Design
Sitanshu Jain, M. Balakrishnan, Anshul Kumar, Shashi Kumar
1997 Misc conf
A Novel Reconfigurable Co-Processor Architecture.
VLSI Design
Gaurav Aggarwal, Nitin Thaper, Kamal Aggarwal, M. Balakrishnan, Shashi Kumar
1997 Misc conf
Allocation of FIFO Structures in RTL Data Paths.
VLSI Design
Heman Khanna, M. Balakrishnan
1997 Misc conf
Optimal Clock Period for Synthesized Data Paths.
VLSI Design
A. R. Naseer, M. Balakrishnan, Anshul Kumar
1995 B conf
Buffer constraints in a variable-rate packetized video system.
ICIP
M. Balakrishnan
1995 B conf
Delay Minimal Mapping of RTL Structures onto LUT Based FPGAs.
FPL
A. R. Naseer, M. Balakrishnan, Anshul Kumar
1995 Misc conf
Heuristic search based approach to scheduling, allocation and binding in Data Path Synthesis.
VLSI Design
Alok Kumar, Anshul Kumar, M. Balakrishnan
1994 B conf
An Efficient Technique for Mapping RTL Structures onto FPGAs.
FPL
A. R. Naseer, M. Balakrishnan, Anshul Kumar
1994 — conf
Concurrent Search and Insertion in K-Dimensional Height Balanced Trees.
IPPS
Atul Varshneya, B. B. Madan, M. Balakrishnan
1994 Misc conf
FAST: FPGA Targeted RTL Structure Synthesis Technique.
VLSI Design
A. R. Naseer, M. Balakrishnan, Anshul Kumar
1993 Misc conf
DESSERT: Design Space Exploration of RT Level Components.
VLSI Design
M. V. Rao, M. Balakrishnan, Anshul Kumar
1993 Misc conf
High Level Design Experiences with IDEAS.
VLSI Design
C. S. Ajay, M. Balakrishnan, D. Harikrishna, M. Karunakaran, Anshul Kumar, Shashi Kumar, V. Mudgil, A. R. Naseer
1992 Misc conf
Data Path Synthesis With Global Time Constraint.
VLSI Design
Prashant P. Nedungadi, M. Balakrishnan, Anshul Kumar
1989 A* conf
Integrated Scheduling and Binding: A Synthesis Approach for Design Space Exploration.
DAC
M. Balakrishnan, Peter Marwedel
1988 J jnl
A Semantic Approach for Modular Synthesis of VLSI Systems.
Inf. Process. Lett.
M. Balakrishnan, S. Sutarwala, Arun K. Majumdar, Dilip K. Banerji, James G. Linders
1988 J jnl
Allocation of multiport memories in data path synthesis.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
M. Balakrishnan, Arun K. Majumdar, Dilip K. Banerji, James G. Linders, Jayanti C. Majithia
1988 J jnl
Synthesis of decentralised controllers from high level description.
Microprocess. Microprogramming
M. Balakrishnan, Arun K. Majumdar, Dilip K. Banerji, James G. Linders
1986 A* conf
An efficient retargetable microcode generator.
MICRO
M. Balakrishnan, P. C. P. Bhatt, B. B. Madan
1982 Misc conf
A multi-channel microprogrammed FFT processor.
ICASSP
M. Balakrishnan, A. V. S. M. Rao, Rajendar Bahl