M. B. Srinivas

126 papers A 4B 2C 14Misc 14Journal 32Unranked 60

Year	Rank	Type	Title / Venue / Authors
2025	J	`jnl`	A Comparative Study of Performance of Various Deep Learning Models and Their Explainability in Detection of Glaucoma. IEEE Access N. K. Jisy, Sudha Radhika, Sirisha Senthil, M. B. Srinivas
2025	J	`jnl`	Addressing Adversarial Attacks in IoT Using Deep Learning AI Models. IEEE Access Sesibhushana Rao Bommana, Sreehari Veeramachaneni, Syed Ershad Ahmed, M. B. Srinivas
2024	—	`conf`	Bistable Physically Unclonable Function with Dynamic Threshold Voltage. MWSCAS Sesibhushana Rao Bommana, Sreehari Veeramachaneni, M. B. Srinivas
2024	J	`jnl`	Early detection of glaucoma: feature visualization with a deep convolutional network. Comput. methods Biomech. Biomed. Eng. Imaging Vis. N. K. Jisy, Md. Hasnat Ali, Sirisha Senthil, M. B. Srinivas
2024	—	`conf`	SNN-LIF Model for Glaucoma Classification. AICAS Harshiv Chandra, Akash Ghosh, Rahul Singh, M. B. Srinivas
2023	J	`jnl`	Hand gestures recognition using edge computing system based on vision transformer and lightweight CNN. J. Ambient Intell. Humaniz. Comput. Khushi Gupta, Arshdeep Singh, Sreenivasa Reddy Yeduri, M. B. Srinivas, Linga Reddy Cenkeramaddi
2022	J	`jnl`	A 12-bit, 1.1-GS/s, Low-Power Flash ADC. IEEE Trans. Very Large Scale Integr. Syst. Mahesh Kumar Adimulam, M. B. Srinivas
2022	J	`jnl`	Architecture slack exploitation for phase classification and performance estimation in server-class processors. J. Parallel Distributed Comput. Diyanesh Chinnakkonda, Karthick Rajamani, M. B. Srinivas
2022	J	`jnl`	Optimization of Reversible Circuits Using Gate Pair Classification. SN Comput. Sci. P. Sai Phaneendra, Chetan Kumar Vudadha, M. B. Srinivas
2022	J	`jnl`	Techniques to Improve Write and Retention Reliability of STT-MRAM Memory Subsystem. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Saravanan Sethuraman, Venkata Kalyan Tavva, M. B. Srinivas
2021	—	`conf`	'Glaucoma - Automating the Cup-to-Disc Ratio Estimation in Fundus Images by Combining Random Walk Algorithm with Otsu Thresholding'. NER Kotturi Venkata SaiTeja, Ponduru Manoj Kumar, Punnamraju Sarath Chandra, N. K. Jisy, Md. Hasnat Ali, M. B. Srinivas
2021	J	`jnl`	Consumer Technology-Based Solutions for COVID-19. IEEE Consumer Electron. Mag. Himanshu Thapliyal, Katina Michael, Saraju P. Mohanty, M. B. Srinivas, Madhavi K. Ganapathiraju
2021	Misc	`conf`	Object Classification Technique for mmWave FMCW Radars using Range-FFT Features. COMSNETS Jyoti Bhatia, Aveen Dayal, Ajit Jha, Santosh Kumar Vishvakarma, J. Soumya, M. B. Srinivas, Phaneendra K. Yalavarthy, Abhinav Kumar, V. Lalitha, Sagar Koorapati, Linga Reddy Cenkeramaddi
2020	J	`jnl`	A 7-Cell, Stackable, Li-Ion Monitoring and Active/Passive Balancing IC With In-Built Cell Balancing Switches for Electric and Hybrid Vehicles. IEEE Trans. Ind. Informatics Veeresh Babu Vulligaddala, Sandeep Vernekar, Sudhakar Singamala, Ravi Kumar Adusumalli, Vijay Ele, Manfred Brandl, M. B. Srinivas
2020	J	`jnl`	Temperature Aware Adaptations for Improved Read Reliability in STT-MRAM Memory Subsystem. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Saravanan Sethuraman, Venkata Kalyan Tavva, Karthick Rajamani, Chitra K. Subramanian, Kyu-Hyoun Kim, Hillery C. Hunter, M. B. Srinivas
2019	J	`jnl`	A frequency domain beamspace adaptive receive beamformer for ultrasound imaging systems: phantom simulation results. Signal Image Video Process. Avinash S. Vaidya, M. B. Srinivas
2019	J	`jnl`	An Improved Logarithmic Multiplier for Media Processing. J. Signal Process. Syst. Syed Ershad Ahmed, M. B. Srinivas
2019	J	`jnl`	Levin's Transformation-based Continuous-Time Linear-Phase Selective Filters. Circuits Syst. Signal Process. Goutham Makkena, M. B. Srinivas
2018	J	`jnl`	A Digitally Calibrated Bandgap Reference With 0.06% Error for Low-Side Current Sensing Application. IEEE J. Solid State Circuits Veeresh Babu Vulligaddala, Ravikumar Adusumalli, Sudhakar Singamala, M. B. Srinivas
2018	Misc	`conf`	An Ultra Low Power, 10-Bit Two-Step Flash ADC for Signal Processing Applications. VLSID Mahesh Kumar Adimulam, Amit Kapoor, Sreehari Veeramachaneni, M. B. Srinivas
2018	—	`conf`	Design Methodologies for Ternary Logic Circuits. ISMVL Chetan Kumar Vudadha, M. B. Srinivas
2018	—	`conf`	Design of Software and Data Analytics for Self-Powered Wireless IoT Devices. iSES Linga Reddy Cenkeramaddi, Ashish Goyal, Asheesh Bhuria, M. B. Srinivas, J. Soumya
2018	J	`jnl`	Energy efficient design of CNFET-based multi-digit ternary adders. Microelectron. J. Chetan Kumar Vudadha, Sai Phaneendra Parlapalli, M. B. Srinivas
2018	J	`jnl`	Improved designs of digit-by-digit decimal multiplier. Integr. Syed Ershad Ahmed, Ch. Santosh Varma, M. B. Srinivas
2018	J	`jnl`	Nonlinear Sequence Transformation-Based Continuous-Time Wavelet Filter Approximation. Circuits Syst. Signal Process. Goutham Makkena, M. B. Srinivas
2018	J	`jnl`	Synthesis of Ternary Logic Circuits Using 2: 1 Multiplexers. IEEE Trans. Circuits Syst. I Regul. Pap. Chetan Kumar Vudadha, Ajay Surya, Saurabh Agrawal, M. B. Srinivas
2017	—	`conf`	A 0.32 µW, 76.8 dB SNDR Programmable Gain Instrumentation Amplifier for Bio-Potential Signal Processing Applications. ISVLSI Mahesh Kumar Adimulam, Krishna Kumar Movva, K. Kolluru, M. B. Srinivas
2017	Misc	`conf`	A Switched-Capacitor Amplifier with True Rail-to-Rail Input Range without Using a Rail-to-Rail Op-Amp. VLSID Anjali Gopinath, Ravi Kumar Adusumalli, Veeresh Babu Vulligaddala, M. B. Srinivas
2017	—	`conf`	A low power, low noise Programmable Analog Front End (PAFE) for biopotential measurements. EMBC Mahesh Kumar Adimulam, Adimulam Divya, K. Tejaswi, M. B. Srinivas
2017	—	`conf`	A low power, programmable 12-bit two step SAR-flash ADC for signal processing applications. SoCC Mahesh Kumar Adimulam, Krishna Kumar Movva, M. B. Srinivas
2017	C	`conf`	A low power, programmable bias inverter quantizer (BIQ) flash ADC. VLSI-SoC Mahesh Kumar Adimulam, Krishna Kumar Movva, Amit Kapoor, M. B. Srinivas
2017	C	`conf`	An ESOP Based Cube Decomposition Technique for Reversible Circuits. RC Sai Phaneendra Parlapalli, Chetan Kumar Vudadha, M. B. Srinivas
2017	C	`conf`	Optimizing the Reversible Circuits Using Complementary Control Line Transformation. RC Sai Phaneendra Parlapalli, Chetan Kumar Vudadha, M. B. Srinivas
2017	—	`conf`	T2A: Analog and RF circuits. SoCC M. B. Srinivas
2017	—	`conf`	Ultra Low Power Programmable Wireless ExG SoC Design for IoT Healthcare System. MobiHealth Mahesh Kumar Adimulam, M. B. Srinivas
2016	Misc	`conf`	A Hybrid Energy Efficient Digital Comparator. VLSID Syed Ershad Ahmed, S. Sweekruth Srinivas, M. B. Srinivas
2016	J	`jnl`	A Soft Computing Approach for Data Routing in Hospital Area Networks (HAN). Int. J. Bus. Data Commun. Netw. Rakhee, M. B. Srinivas
2016	—	`conf`	An Efficient Design Methodology for CNFET Based Ternary Logic Circuits. iNIS Chetan Kumar Vudadha, P. Sai Phaneendra, M. B. Srinivas
2016	C	`conf`	An Iterative Logarithmic Multiplier with Improved Precision. ARITH Syed Ershad Ahmed, Sanket Kadam, M. B. Srinivas
2016	—	`conf`	Modeling of EXG (ECG, EMG and EEG) non-idealities using MATLAB. CISP-BMEI Mahesh Kumar Adimulam, M. B. Srinivas
2014	Misc	`conf`	A Decimal/Binary Multi-operand Adder Using a Fast Binary to Decimal Converter. VLSID Ch. Santosh Varma, Syed Ershad Ahmed, M. B. Srinivas
2014	Misc	`conf`	A Novel Low Power Error Detection Logic for Inexact Leading Zero Anticipator in Floating Point Units. VLSID B. Naveen Kumar Reddy, M. Chandra Sekhar, Sreehari Veeramachaneni, M. B. Srinivas
2014	—	`conf`	A reconfigurable 0-L1-L2 S-MASH SoCC Abhilash K. N, M. B. Srinivas
2014	—	`conf`	A unified flagged prefix constant addition-subtraction scheme for design of area and power efficient binary floating-point and constant integer arithmetic circuits. APCCAS Soumya Ganguly, Abhishek Mittal, Syed Ershad Ahmed, M. B. Srinivas
2014	Misc	`conf`	An Optimized Design of Reversible Quantum Comparator. VLSID P. Sai Phaneendra, Chetan Kumar Vudadha, Sreehari Veeramachaneni, M. B. Srinivas
2014	—	`conf`	Estimation of Arterial Stiffness through Pulse Transit Time Measurement. BIODEVICES Avinash S. Vaidya, T. S. L. Radhika, M. B. Srinivas, Mannan Mridha
2013	—	`conf`	A smart phone/tablet based mobile health care system for developing countries. EMBC Avinash S. Vaidya, M. B. Srinivas, P. Himabindu, Daria Jumaxanova
2013	—	`conf`	Uniform approximation of Gaussian wavelet for biomedical signal processing in analog domain. EMBC Goutham Makkena, Prabhakara Rao, M. B. Srinivas
2012	—	`conf`	A Modified Twin Precision Multiplier with 2D Bypassing Technique. ISED Syed Ershad Ahmed, Sibi Abraham, Sreehari Veeramachaneni, N. Moorthy Muthukrishnan, M. B. Srinivas
2012	—	`conf`	CNFET based ternary magnitude comparator. ISCIT Chetan Kumar Vudadha, Phaneendra P. Sai, Sreehari Veeramachaneni, M. B. Srinivas
2012	Misc	`conf`	Low-Power Self Reconfigurable Multiplexer Based Decoder for Adaptive Resolution Flash ADCs. VLSI Design Chetan Kumar Vudadha, Goutham Makkena, M. Venkata Swamy Nayudu, P. Sai Phaneendra, Syed Ershad Ahmed, Sreehari Veeramachaneni, N. Moorthy Muthukrishnan, M. B. Srinivas
2012	—	`conf`	On the Suitability of Multi-Core Processing for Embedded Automotive Systems. CyberC Santosh Kumar Jena, M. B. Srinivas
2011	—	`conf`	A Multiple-Bandwidth 10-bit SAR Analog to Digital Converter. ISED Mahesh Kumar Adimulam, Krishna Kumar Movva, Sreehari Veeramachaneni, N. Moorthy Muthukrishnan, M. B. Srinivas
2011	—	`conf`	A Prefix Based Reconfigurable Adder. ISVLSI Chetan Kumar V., Sai Phaneendra P., Syed Ershad Ahmed, Sreehari Veeramachaneni, N. Moorthy Muthukrishnan, M. B. Srinivas
2011	—	`conf`	A Reconfigurable INC/DEC/2's Complement/Priority Encoder Circuit with Improved Decision Block. ISED Chetan Kumar V., P. Sai Phaneendra, Syed Ershad Ahmed, Sreehari Veeramachaneni, N. Moorthy Muthukrishnan, M. B. Srinivas
2011	C	`conf`	A Unified Architecture for BCD and Binary Adder/Subtractor. DSD Chetan Kumar V., P. Sai Phaneendra, Syed Ershad Ahmed, Sreehari Veeramachaneni, N. Moorthy Muthukrishnan, M. B. Srinivas
2011	—	`conf`	Increment/decrement/2's complement/priority encoder circuit for varying operand lengths. ISCIT P. Sai Phaneendra, Chetan Kumar Vudadha, Syed Ershad Ahmed, Sreehari Veeramachaneni, N. Moorthy Muthukrishnan, M. B. Srinivas
2010	—	`conf`	A Novel, Variable Resolution Flash ADC with Sub Flash Architecture. ISVLSI Mahesh Kumar Adimulam, Sreehari Veeramachaneni, N. Moorthy Muthukrishnan, M. B. Srinivas
2010	—	`conf`	A low power, variable resolution two-step flash ADC. ACM Great Lakes Symposium on VLSI Mahesh Kumar Adimulam, Krishna Kumar Movva, Sreehari Veeramachaneni, N. Moorthy Muthukrishnan, M. B. Srinivas
2010	—	`conf`	A new approach to minimize leakage power in nano-scale VLSI adder. ICWET Pradeep Jamwal, M. B. Srinivas, G. V. K. Sarma, M. Murali Krishna
2010	J	`jnl`	An Alternate Approach to Buffer Insertion for Delay and Power Reduction in VLSI Interconnects. J. Low Power Electron. Sandeep Saini, A. Mahesh Kumar, Sreehari Veeramachaneni, M. B. Srinivas
2010	Misc	`conf`	An Alternative approach to Buffer Insertion for Delay and Power Reduction in VLSI Interconnects. VLSI Design Sandeep Saini, Mahesh Kumar Adimulam, Sreehari Veeramachaneni, M. B. Srinivas
2010	—	`conf`	An efficient ODT calibration scheme for improved signal integrity in memory interface. APCCAS Gudipati Kalyan, M. B. Srinivas
2009	—	`conf`	A High Performance Unified BCD and Binary Adder/Subtractor. ISVLSI Anshul Singh, Aman Gupta, Sreehari Veeramachaneni, M. B. Srinivas
2009	J	`jnl`	A Novel Low Power, Variable Resolution Flash Analog-to-Digital Converter. J. Low Power Electron. Mahesh Kumar Adimulam, Sreehari Veeramachaneni, M. B. Srinivas
2009	—	`conf`	A novel low power, variable resolution pipelined ADC. SoCC Mahesh Kumar Adimulam, Sreehari Veeramachaneni, M. B. Srinivas
2009	—	`conf`	All Digital Duty Cycle Correction Circuit in 90nm Based on Mutex. ISVLSI Swathi Ramasahayam, M. B. Srinivas
2009	Misc	`conf`	Design of a Low Power, Variable-Resolution Flash ADC. VLSI Design Sreehari Veeramachaneni, Mahesh Kumar Adimulam, Venkat Tummala, M. B. Srinivas
2009	J	`jnl`	Efficient Reversible Logic Design of BCD Subtractors. Trans. Comput. Sci. Himanshu Thapliyal, Hamid R. Arabnia, M. B. Srinivas
2009	B	`conf`	Multi-hop scheduling and local data link aggregation dependant Qos in modeling and simulation of power-aware wireless sensor networks. IWCMC Vasanth Iyer, S. Sitharama Iyengar, Garimella Rama Murthy, Bertrand Hochet, Vir V. Phoha, M. B. Srinivas
2008	Misc	`conf`	A Novel Carry-Look Ahead Approach to a Unified BCD and Binary Adder/Subtractor. VLSI Design Sreehari Veeramachaneni, Kirthi M. Krishna, Prateek G. V., Subroto S., Bharat S., M. B. Srinivas
2008	—	`conf`	A Novel Encoding Scheme for Delay and Energy Minimization in VLSI Interconnects with Built-In Error Detection. ISVLSI Lingamneni Avinash, Kirthi Krishna Muntimadugu, M. B. Srinivas
2008	—	`conf`	Generic sub-space algorithm for generating reduced order models of linear time varying vlsi circuits. ACM Great Lakes Symposium on VLSI J. V. R. Ravindra, M. B. Srinivas
2008	—	`conf`	Process Variation Aware Bus-Coding Scheme for Delay Minimization in VLSI Interconnects. ISQED Chittarsu Raghunandan, K. S. Sainarayanan, M. B. Srinivas
2008	—	`conf`	Training Data Compression Algorithms and Reliability in Large Wireless Sensor Networks. SUTC Vasanth Iyer, Rammurthy Garimella, M. B. Srinivas
2007	—	`conf`	A Comparative Study of Different FFT Architectures for Software Defined Radio. SAMOS Shashank Mittal, Md. Zafar Ali Khan, M. B. Srinivas
2007	C	`conf`	A Statistical Model for Estimating the Effect of Process Variations on Delay and Slew Metrics for VLSI Interconnects. DSD J. V. R. Ravindra, M. B. Srinivas
2007	Misc	`conf`	A Unified, Reconfigurable Architecture for Montgomery Multiplication in Finite Fields GF(p) and GF(2^n). VLSI Design M. Sudhakar, Ramachandruni Venkata Kamala, M. B. Srinivas
2007	C	`conf`	A bit-sliced, scalable and unified montgomery multiplier architecture for RSA and ECC. VLSI-SoC M. Sudhakar, Ramachandruni Venkata Kamala, M. B. Srinivas
2007	—	`conf`	A unified and reconfigurable Montgomery Multiplier architecture without four-to-two CSA. SBCCI Sudhakar Maddi, M. B. Srinivas
2007	C	`conf`	Area Efficient Bus Encoding Technique for Minimizing Simultaneous Switching Noise (SSN). ISCAS Chittarsu Raghunandan, K. S. Sainarayanan, M. B. Srinivas
2007	B	`conf`	Area Efficient High Speed Architecture of Bruun's FFT for Software Defined Radio. GLOBECOM Shashank Mittal, Md. Zafar Ali Khan, M. B. Srinivas
2007	—	`conf`	Bus encoding schemes for minimizing delay in VLSI interconnects. SBCCI K. S. Sainarayanan, Chittarsu Raghunandan, M. B. Srinivas
2007	—	`conf`	Bus-encoding technique to reduce delay, power and simultaneous switching noise (SSN) in RLC interconnects. ACM Great Lakes Symposium on VLSI Chittarsu Raghunandan, K. S. Sainarayanan, M. B. Srinivas
2007	J	`jnl`	Delay and Energy Efficient Coding Techniques for Capacitive Interconnects. J. Circuits Syst. Comput. J. V. R. Ravindra, M. B. Srinivas
2007	—	`conf`	Delay and Power Minimization in VLSI Interconnects with Spatio-Temporal Bus-Encoding Scheme. ISVLSI K. S. Sainarayanan, Chittarsu Raghunandan, M. B. Srinivas
2007	—	`conf`	Generating reduced order models using subspace iteration for linear RLC circuits in nanometer designs. Nano-Net J. V. R. Ravindra, M. B. Srinivas
2007	J	`jnl`	New and Improved Architectures for Montgomery Modular Multiplication. Mob. Networks Appl. M. Sudhakar, Ramachandruni Venkata Kamala, M. B. Srinivas
2007	Misc	`conf`	Novel Architectures for High-Speed and Low-Power 3-2, 4-2 and 5-2 Compressors. VLSI Design Sreehari Veeramachaneni, Kirthi M. Krishna, Lingamneni Avinash, Reddy Puppala Sreekanth, M. B. Srinivas
2007	C	`conf`	Novel High-Speed Redundant Binary to Binary converter using Prefix Networks. ISCAS Sreehari Veeramachaneni, Kirthi M. Krishna, Lingamneni Avinash, Reddy Puppala Sreekanth, M. B. Srinivas
2007	—	`conf`	Novel architectures for efficient (m, n) parallel counters. ACM Great Lakes Symposium on VLSI Sreehari Veeramachaneni, Lingamneni Avinash, Kirthi M. Krishna, M. B. Srinivas
2007	—	`conf`	Novel, High-Speed 16-Digit BCD Adders Conforming to IEEE 754r Format. ISVLSI Sreehari Veeramachaneni, Kirthi M. Krishna, Lingamneni Avinash, Reddy Puppala Sreekanth, M. B. Srinivas
2007	—	`conf`	Rule Selection in Fuzzy Systems using Heuristics and Branch Prediction. FOCI Keerthi Laal Kala, M. B. Srinivas
2006	—	`conf`	A Generic Architecture for Intelligent System Hardware. APCCAS Keerthi Laal Kala, M. B. Srinivas
2006	J	`jnl`	A New Reversible TSG Gate and Its Application For Designing Efficient Adder Circuits CoRR Himanshu Thapliyal, M. B. Srinivas
2006	C	`conf`	A novel, coupling driven, low power bus coding technique for minimizing capacitive crosstalk in VLSI interconnects. ISCAS K. S. Sainarayanan, J. V. R. Ravindra, M. B. Srinivas
2006	C	`conf`	An Efficient Reconfigurable Montgomery Multiplier Architecture for GF(n). DSD Ramachandruni Venkata Kamala, M. Sudhakar, M. B. Srinivas
2006	J	`jnl`	An Extension to DNA Based Fredkin Gate Circuits: Design of Reversible Sequential Circuits using Fredkin Gates CoRR Himanshu Thapliyal, M. B. Srinivas
2006	C	`conf`	High-Throughput Montgomery Modular Multiplication. VLSI-SoC Ramachandruni Venkata Kamala, M. B. Srinivas
2006	C	`conf`	Low Power Hierarchical Multiplier and Carry Look-Ahead Architecture. AICCSA Himanshu Thapliyal, Neela Gopi, K. K. Pavan Kumar, M. B. Srinivas
2006	—	`conf`	Minimizing Simultaneous Switching Noise (SSN) using Modified Odd/Even Bus Invert Method. DELTA K. S. Sainarayanan, J. V. R. Ravindra, M. B. Srinivas
2006	—	`conf`	Modified Montgomery Modular Multiplication Using 4: 2 Compressor and CSA Adder. DELTA Himanshu Thapliyal, Anvesh Ramasahayam, Vivek Reddy Kotha, Kunul Gottimukkula, M. B. Srinivas
2006	J	`jnl`	Novel BCD Adders and Their Reversible Logic Implementation for IEEE 754r Format CoRR Himanshu Thapliyal, Saurabh Kotiyal, M. B. Srinivas
2006	Misc	`conf`	Novel BCD Adders and Their Reversible Logic Implementation for IEEE 754r Format. VLSI Design Himanshu Thapliyal, Saurabh Kotiyal, M. B. Srinivas
2006	J	`jnl`	Novel Reversible Multiplier Architecture Using Reversible TSG Gate CoRR Himanshu Thapliyal, M. B. Srinivas
2006	C	`conf`	Novel Reversible Multiplier Architecture Using Reversible TSG Gate. AICCSA Himanshu Thapliyal, M. B. Srinivas
2006	J	`jnl`	Novel Reversible TSG Gate and Its Application for Designing Components of Primitive Reversible/Quantum ALU CoRR Himanshu Thapliyal, M. B. Srinivas
2006	A	`conf`	Novel and Efficient 4: 2 and 5: 2 Compressors with Minimum Number of Transistors Designed for Low-Power Operations. ESA Pallavi Devi Gopineedi, Himanshu Thapliyal, M. B. Srinivas, Hamid R. Arabnia
2006	J	`jnl`	Reduced Area Low Power High Throughput BCD Adders for IEEE 754r Format CoRR Himanshu Thapliyal, Hamid R. Arabnia, M. B. Srinivas
2006	—	`conf`	The New BCD Subtractor and Its Reversible Logic Implementation. Asia-Pacific Computer Systems Architecture Conference Himanshu Thapliyal, M. B. Srinivas
2006	J	`jnl`	VLSI Implementation of RSA Encryption System Using Ancient Indian Vedic Mathematics CoRR Himanshu Thapliyal, M. B. Srinivas
2005	—	`conf`	A 32-Bit Binary Floating Point Neuro-Chip. ICNC (3) Keerthi Laal Kala, M. B. Srinivas
2005	A	`conf`	A Need of Quantum Computing: Reversible Logic Synthesis of Parallel Binary Adder-Subtractor. ESA Himanshu Thapliyal, M. B. Srinivas, Hamid R. Arabnia
2005	—	`conf`	A Novel Reversible TSG Gate and Its Application for Designing Reversible Carry Look-Ahead and Other Adder Architectures. Asia-Pacific Computer Systems Architecture Conference Himanshu Thapliyal, M. B. Srinivas
2005	A	`conf`	A Reversible Version of 4 x 4 Bit Array Multiplier With Minimum Gates and Garbage Outputs. ESA Himanshu Thapliyal, M. B. Srinivas, Hamid R. Arabnia
2005	—	`conf`	A novel deep submicron low power bus coding technique. Circuits, Signals, and Systems K. S. Sainarayanan, J. V. R. Ravindra, M. B. Srinivas
2005	—	`conf`	Design And Analysis of A VLSI Based High Performance Low Power Parallel Square Architecture. AMCS Himanshu Thapliyal, M. B. Srinivas, Hamid R. Arabnia
2005	—	`conf`	Design for A Fast And Low Power 2's Complement Multiplier. CDES Himanshu Thapliyal, M. B. Srinivas, Hamid R. Arabnia
2005	—	`conf`	Faster RSA Encryption/Decryption Architecture Using an Efficient High Speed Overlay Multiplier. Security and Management Himanshu Thapliyal, M. B. Srinivas, Hamid R. Arabnia
2005	—	`conf`	Implementation of A Fast Square In RSA Encryption/Decryption Architecture. Security and Management Himanshu Thapliyal, M. B. Srinivas, Hamid R. Arabnia
2005	—	`conf`	Local Language Support for Handheld Devices. ITCC (2) Yaswanth Narvaneni, M. B. Srinivas
2005	A	`conf`	Reversible Logic Synthesis of Half, Full and Parallel Subtractors. ESA Himanshu Thapliyal, M. B. Srinivas, Hamid R. Arabnia
2005	—	`conf`	VLSI Implementation of O(n*n) Sorting Algorithms And Their Hardware Comparison. CSC Saurabh Kotiyal, Himanshu Thapliyal, M. B. Srinivas, Hamid R. Arabnia
2005	—	`conf`	Verilog Coding Style for Efficient Synthesis In FPGA. CDES Himanshu Thapliyal, M. B. Srinivas, Rameshwar Rao, Hamid R. Arabnia
2003	—	`conf`	Design of a digital CDMA receiver. ASP-DAC I. Vijay Kumar, M. B. Srinivas
2003	—	`conf`	Speech encoding and encryption in VLSI. ASP-DAC K. Kalyan Chakravarthy, M. B. Srinivas