Luís Miguel Silveira

65 papers A* 8A 20B 1C 4Misc 1Journal 20Unranked 9

Year	Rank	Type	Title / Venue / Authors
2024	—	`conf`	Echo State Networks for Accurate and Efficient Modeling of Dynamic Circuits. AICAS Paulo Machado, Ruxandra Barbulescu, Luís Miguel Silveira
2023	B	`conf`	EUROPULS: NEUROmorphic energy-efficient secure accelerators based on Phase change materials aUgmented siLicon photonicS. ETS Fabio Pavanello, Cédric Marchand, Ian O'Connor, Régis Orobtchouk, Fabien Mandorlo, Xavier Letartre, Sébastien Cueff, Elena-Ioana Vatajelu, Giorgio Di Natale, Benoit Cluzel, Aurelien Coillet, Benoît Charbonnier, Pierre Noe, Frantisek Kavan, Martin Zoldak, Michal Szaj, Peter Bienstman, Thomas Van Vaerenbergh, Ulrich Rührmair, Paulo F. Flores, Luís Guerra e Silva, Ricardo Chaves, Luís Miguel Silveira, Mariano Ceccato, Dimitris Gizopoulos, George Papadimitriou, Vasileios Karakostas, Axel Brando, Francisco J. Cazorla, Ramon Canal, Pau Closas, Adria Gusi-Amigo, Paolo Crovetti, Alessio Carpegna, Tzamn Melendez Carmona, Stefano Di Carlo, Alessandro Savino
2023	J	`jnl`	NEUROPULS: NEUROmorphic energy-efficient secure accelerators based on Phase change materials aUgmented siLicon photonicS. CoRR Fabio Pavanello, Cédric Marchand, Ian O'Connor, Régis Orobtchouk, Fabien Mandorlo, Xavier Letartre, Sébastien Cueff, Elena-Ioana Vatajelu, Giorgio Di Natale, Benoit Cluzel, Aurelien Coillet, Benoît Charbonnier, Pierre Noe, Frantisek Kavan, Martin Zoldak, Michal Szaj, Peter Bienstman, Thomas Van Vaerenbergh, Ulrich Rührmair, Paulo F. Flores, Luís Guerra e Silva, Ricardo Chaves, Luís Miguel Silveira, Mariano Ceccato, Dimitris Gizopoulos, George Papadimitriou, Vasileios Karakostas, Axel Brando, Francisco J. Cazorla, Ramon Canal, Pau Closas, Adria Gusi-Amigo, Paolo Crovetti, Alessio Carpegna, Tzamn Melendez Carmona, Stefano Di Carlo, Alessandro Savino
2019	J	`jnl`	Reduced order models of myelinated axonal compartments. J. Comput. Neurosci. Daniel Ioan, Ruxandra Barbulescu, Luís Miguel Silveira, Gabriela Ciuprina
2017	J	`jnl`	Circuit Synthesis for Guaranteed Positive Sparse Realization of Passive State-Space Models. IEEE Trans. Circuits Syst. I Regul. Pap. Jorge Fernandez Villena, Luís Miguel Silveira
2016	—	`conf`	Physiological noise model comparison for resting-state fMRI at 7 T. ISBI Sandro Nunes, Marta Bianciardi, Afonso Dias, Luís Miguel Silveira, Lawrence L. Wald, Patrícia Figueiredo
2016	A	`conf`	Variability and statistical analysis flow for dynamic linear systems with large number of inputs. DATE A. Lucas Martins, Jorge Fernandez Villena, Luís Miguel Silveira
2015	—	`ed.`	VLSI-SoC: At the Crossroads of Emerging Trends - 21st IFIP WG 10.5/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2013, Istanbul, Turkey, October 6-9, 2013, Revised and Extended Selected Papers VLSI-SoC (Selected Papers) Alex Orailoglu, H. Fatih Ugurdag, Luís Miguel Silveira, Martin Margala, Ricardo Reis
2013	C	`ed.`	21st IEEE/IFIP International Conference on VLSI and System-on-Chip, VLSI-SoC 2013, Istanbul, Turkey, October 7-9, 2013 VLSI-SoC Martin Margala, Ricardo Augusto da Luz Reis, Alex Orailoglu, Luigi Carro, Luís Miguel Silveira, H. Fatih Ugurdag
2012	J	`jnl`	Exploiting Parallelism for Improved Automation of Multidimensional Model Order Reduction. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Jorge Fernandez Villena, Luís Miguel Silveira
2011	A	`conf`	Fast statistical analysis of RC nets subject to manufacturing variabilities. DATE Yu Bi, Kees-Jan van der Kolk, Jorge Fernandez Villena, Luís Miguel Silveira, Nick van der Meijs
2011	—	`conf`	Handling intra-die variations in PSTA. ACM Great Lakes Symposium on VLSI Luís Guerra e Silva, Luís Miguel Silveira
2010	A	`conf`	3POr - Parallel projection based parameterized order reduction for multi-dimensional linear models. ICCAD Jorge Fernandez Villena, Luís Miguel Silveira
2010	J	`jnl`	Effective Corner-Based Techniques for Variation-Aware IC Timing Verification. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Luís Guerra e Silva, Joel R. Phillips, Luís Miguel Silveira
2010	J	`jnl`	Efficient Simulation of Power Grids. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. João M. S. Silva, Joel R. Phillips, Luís Miguel Silveira
2010	A	`conf`	HORUS - high-dimensional Model Order Reduction via low moment-matching upgraded sampling. DATE Jorge Fernandez Villena, Luís Miguel Silveira
2010	J	`jnl`	SPARE - A Scalable Algorithm for Passive, Structure Preserving, Parameter-Aware Model Order Reduction. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Jorge Fernandez Villena, Luís Miguel Silveira
2009	A*	`conf`	ARMS - automatic residue-minimization based sampling for multi-point modeling techniques. DAC Jorge Fernandez Villena, Luís Miguel Silveira
2009	A	`conf`	Fast and reliable passivity assessment and enforcement with extended Hamiltonian pencil. ICCAD Zuochang Ye, Luís Miguel Silveira, Joel R. Phillips
2009	A	`conf`	On the efficient reduction of complete EM based parametric models. DATE Jorge Fernandez Villena, Gabriela Ciuprina, Daniel Ioan, Luís Miguel Silveira
2009	J	`jnl`	PMSat: a parallel version of MiniSAT. J. Satisf. Boolean Model. Comput. Luís Gil, Paulo F. Flores, Luís Miguel Silveira
2009	C	`conf`	Power Macro-Modeling Using an Iterative LS-SVM Method. VLSI-SoC António Gusmão, Luís Miguel Silveira, José Monteiro
2008	A	`conf`	Efficient Representation and Analysis of Power Grids. DATE João M. S. Silva, Joel R. Phillips, Luís Miguel Silveira
2008	—	`conf`	Generating Worst-Case Stimuli for Accurate Power Grid Analysis. PATMOS Pedro Marques Morgado, Paulo F. Flores, José C. Monteiro, Luís Miguel Silveira
2008	A	`conf`	SPARE - a Scalable algorithm for passive, structure preserving, Parameter-Aware model order REduction. DATE Jorge Fernandez Villena, Luís Miguel Silveira
2007	J	`jnl`	Dynamic models for substrate coupling in mixed-mode systems. IET Circuits Devices Syst. João M. S. Silva, Luís Miguel Silveira
2007	A	`conf`	Efficient computation of the worst-delay corner. DATE Luís Guerra e Silva, Luís Miguel Silveira, Joel R. Phillips
2006	J	`jnl`	Generating High-Accuracy Simulation Models Using Problem-Tailored Orthogonal Polynomials Basis. IEEE Trans. Circuits Syst. I Regul. Pap. Carlos P. Coelho, Joel R. Phillips, Luís Miguel Silveira
2006	J	`jnl`	Resampling Plans for Sample Point Selection in Multipoint Model-Order Reduction. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Luís Miguel Silveira, Joel R. Phillips
2005	C	`conf`	Grid-based statistical timing analysis. IADIS AC Luís Guerra e Silva, Luís Miguel Silveira
2005	J	`jnl`	Poor man's TBR: a simple model reduction scheme. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Joel R. Phillips, Luís Miguel Silveira
2004	J	`jnl`	A convex programming approach for generating guaranteed passive approximations to tabulated frequency-data. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Carlos P. Coelho, Joel R. Phillips, Luís Miguel Silveira
2004	A*	`conf`	Exploiting input information in a model reduction algorithm for massively coupled parasitic networks. DAC Luís Miguel Silveira, Joel R. Phillips
2004	—	`conf`	Multigrid-based substrate coupling model extraction. ISCAS (5) João M. S. Silva, Luís Miguel Silveira
2004	A	`conf`	Poor Man's TBR: A Simple Model Reduction Scheme. DATE Joel R. Phillips, Luís Miguel Silveira
2004	J	`jnl`	Power Estimation Using Probability Polynomials. Des. Autom. Embed. Syst. José C. Costa, Luís Miguel Silveira, Srinivas Devadas, José Monteiro
2003	A	`conf`	Analog Macromodeling using Kernel Methods. ICCAD Joel R. Phillips, João Afonso, Arlindo L. Oliveira, Luís Miguel Silveira
2003	C	`conf`	Dynamic Models for Substrate Coupling in Mixed-Mode Systems. VLSI-SOC João M. S. Silva, Luís Miguel Silveira
2003	—	`conf`	Dynamic Models for Substrate Coupling in Mixed-Mode Systems. VLSI-SoC (Selected Papers) João M. S. Silva, Luís Miguel Silveira
2003	J	`jnl`	Guaranteed passive balancing transformations for model order reduction. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Joel R. Phillips, Luca Daniel, Luís Miguel Silveira
2002	J	`jnl`	Characterizing Substrate Coupling in Deep-Submicron Designs. IEEE Des. Test Comput. Luís Miguel Silveira, Nuno Vargas
2002	A*	`conf`	Guaranteed passive balancing transformations for model order reduction. DAC Joel R. Phillips, Luca Daniel, Luís Miguel Silveira
2002	A	`conf`	Optimization based passive constrained fitting. ICCAD Carlos P. Coelho, Joel R. Phillips, Luís Miguel Silveira
2002	A	`conf`	Passive Constrained Rational Approximation Algorithm Using Nevanlinna-Pick Interpolation. DATE Carlos P. Coelho, Luís Miguel Silveira, Joel R. Phillips
2002	J	`jnl`	Satisfiability models and algorithms for circuit delay computation. ACM Trans. Design Autom. Electr. Syst. Luís Guerra e Silva, João Marques-Silva, Luís Miguel Silveira, Karem A. Sakallah
2001	A	`conf`	A Convex Programming Approach to Positive Real Rational Approximation. ICCAD Carlos P. Coelho, Joel R. Phillips, Luís Miguel Silveira
2001	A	`conf`	Simulation Approaches for Strongly Coupled Interconnect Systems. ICCAD Joel R. Phillips, Luís Miguel Silveira
2000	—	`conf`	A benchmark suite for substrate analysis. ASP-DAC Edoardo Charbon, Luís Miguel Silveira, Paolo Miliozzi
1999	A	`conf`	Algorithms for Solving Boolean Satisfiability in Combinational Circuits. DATE Luís Guerra e Silva, Luís Miguel Silveira, João Marques-Silva
1999	J	`jnl`	Efficient techniques for accurate modeling and simulation ofsubstrate coupling in mixed-signal IC's. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. João Paulo Costa, Mike Chou, Luís Miguel Silveira
1999	A*	`conf`	Interconnect Analysis: From 3-D Structures to Circuit Models. DAC Mattan Kamon, Nuno Alexandre Marques, Yehia Massoud, Luís Miguel Silveira, Jacob White
1999	A*	`conf`	Robust Rational Function Approximation Algorithm for Model Generation. DAC Carlos P. Coelho, Joel R. Phillips, Luís Miguel Silveira
1998	A*	`conf`	A Mixed Nodal-Mesh Formulation for Efficient Extraction and Passive Reduced-Order Modeling of 3D Interconnects. DAC Nuno Alexandre Marques, Mattan Kamon, Jacob White, Luís Miguel Silveira
1998	A	`conf`	An Efficient Algorithm for Fast Parasitic Extraction and Passive Order Reduction of 3D Interconnect Models. DATE Nuno Alexandre Marques, Mattan Kamon, Jacob K. White, Luís Miguel Silveira
1998	—	`conf`	Timing analysis using propositional satisfiability. ICECS Luís Guerra e Silva, João P. Marques Silva, Luís Miguel Silveira, Karem A. Sakallah
1996	A	`conf`	A coordinate-transformed Arnoldi algorithm for generating guaranteed stable reduced-order models of RLC circuits. ICCAD Luís Miguel Silveira, Mattan Kamon, Ibrahim M. Elfadel, Jacob White
1996	Misc	`conf`	Stability criteria for Arnoldi-based model-order reduction. ICASSP Ibrahim M. Elfadel, Luís Miguel Silveira, Jacob K. White
1995	A*	`conf`	Efficient Reduced-Order Modeling of Frequency-Dependent Coupling Inductances Associated with 3-D Interconnect Structures. DAC Luís Miguel Silveira, Mattan Kamon, Jacob White
1995	—	`conf`	Efficient reduced-order modeling of frequency-dependent coupling inductances associated with 3-D interconnect structures. ED&TC Luís Miguel Silveira, Mattan Kamon, Jacob K. White
1994	A*	`conf`	An Efficient Approach to Transmission Line Simulation Using Measured or Tabulated S-parameter Data. DAC Luís Miguel Silveira, Ibrahim M. Elfadel, Jacob White, Moni Chilukuri, Kenneth S. Kundert
1994	—	`—`	Model order reduction techniques for circuit simulation. Luís Miguel Silveira
1993	J	`jnl`	Massively parallel simulation algorithms for grid-based analog signal processors. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Andrew Lumsdaine, Luís Miguel Silveira, Jacob K. White
1992	J	`jnl`	On exponential fitting for circuit simulation. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Luís Miguel Silveira, Jacob K. White, Horácio C. Neto, Luís M. Vidigal
1991	A	`conf`	A Modified Envelope-Following Approach to Clocked Analog Circuit Simulation. ICCAD Luís Miguel Silveira, Jacob White, Steven B. Leeb
1990	A	`conf`	Parallel Simulation Algorithms for Grid-Based Analog Signal Processors. ICCAD Luís Miguel Silveira, Andrew Lumsdaine, Jacob White