Luz Balado

19 papers A 1B 2C 1Misc 1Journal 8Unranked 6
YearRankTypeTitle / Venue / Authors
2020 J jnl
Indirect and adaptive test of analogue circuits based on preselected steady-state response measures.
IET Circuits Devices Syst.
Álvaro Gómez-Pau, Emili Lupon, Luz Balado, Joan Figueras
2017 J jnl
Multi-Directional Space Tessellation to Improve the Decision Boundary in Indirect Mixed-Signal Testing.
J. Electron. Test.
Álvaro Gómez-Pau, Luz Balado, Joan Figueras
2016 J jnl
Efficient Production Binning Using Octree Tessellation in the Alternate Measurements Space.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Álvaro Gómez-Pau, Luz Balado, Joan Figueras
2016 J jnl
Indirect test of M-S circuits using multiple specification band guarding.
Integr.
Álvaro Gómez-Pau, Luz Balado, Joan Figueras
2015 — conf
Analog circuits testing using digitally coded indirect measurements.
DTIS
Álvaro Gómez-Pau, Luz Balado, Joan Figueras
2014 B conf
M-S specification binning based on digitally coded indirect measurements.
ETS
Álvaro Gómez-Pau, Luz Balado, Joan Figueras
2013 B conf
M-S test based on specification validation using octrees in the measure space.
ETS
Álvaro Gómez-Pau, Luz Balado, Joan Figueras
2010 A conf
Analog circuit test based on a digital signature.
DATE
Alvaro Gómez, Ricard Sanahuja, Luz Balado, Joan Figueras
2009 J jnl
Verifying Functional Specifications by Regression Techniques on Lissajous Test Signatures.
IEEE Trans. Circuits Syst. I Regul. Pap.
Luz Balado, Emili Lupon, Joan Figueras, Miquel Roca, Eugeni Isern, Rodrigo Picos
2006 C conf
Lissajous Based Mixed-Signal Testing for N-Observable Signals.
DDECS
Luz Balado, Emili Lupon, L. García, Rosa Rodríguez-Montañés, Joan Figueras
2005 J jnl
Testing Biquad Filters under Parametric Shifts Using X-Y Zoning.
J. Electron. Test.
R. Sanahuja, Victor Barcons, Luz Balado, Joan Figueras
2004 J jnl
Analog Switches in Programmable Analog Devices: Quiescent Defective Behaviours.
J. Electron. Test.
Rosa Rodríguez-Montañés, D. Muñoz, Luz Balado, Joan Figueras
2004 Misc conf
BIST Technique by Equally Spaced Test Vector Sequences.
VTS
Salvador Manich, L. García, Luz Balado, Emili Lupon, Josep Rius, Rosa Rodríguez-Montañés, Joan Figueras
2004 — conf
Digital, Memory and Mixed-Signal Test Engineering Education: Five Centres of Competence in Europ.
DELTA
Marie-Lise Flottes, Yves Bertrand, Luz Balado, Emili Lupon, Anton Biasizzo, Franc Novak, Stefano Di Carlo, Paolo Prinetto, Nicoleta Pricopi, Hans-Joachim Wunderlich
2004 J jnl
On High-Quality, Low Energy Built-In Self Test Preparation at RT-Level.
J. Electron. Test.
Marcelino B. Santos, Isabel C. Teixeira, João Paulo Teixeira, Salvador Manich, Luz Balado, Joan Figueras
2003 — conf
On the selection of efficient arithmetic additive test pattern generators [logic test].
ETW
Salvador Manich, L. García, Luz Balado, Emili Lupon, Josep Rius, Rosa Rodríguez-Montañés, Joan Figueras
2003 — conf
Test Engineering Education in Europe: the EuNICE-Test Project.
MSE
Yves Bertrand, Marie-Lise Flottes, Luz Balado, Joan Figueras, Anton Biasizzo, Franc Novak, Stefano Di Carlo, Paolo Prinetto, Nicoleta Pricopi, Hans-Joachim Wunderlich, Jean-Pierre Van der Heyden
2002 — conf
Analog Switches in Programmable Analog Devices: Quiescent Defective Behaviours.
IOLTW
Rosa Rodríguez-Montañés, D. Muñoz, Luz Balado, Joan Figueras
2002 — conf
On High-Quality, Low Energy BIST Preparation at RT-Level.
LATW
Marcelino B. Santos, Isabel C. Teixeira, João Paulo Teixeira, Salvador Manich, Luz Balado, Joan Figueras