Lun-Yao Wang

19 papers C 2Journal 11Unranked 6
YearRankTypeTitle / Venue / Authors
2020 J jnl
A High-Performance Design of Generalized Pipeline Cellular Array.
IEEE Comput. Archit. Lett.
Zhufei Chu, Huiming Tian, Zeqiang Li, Yinshui Xia, Lun-Yao Wang
2020 J jnl
Advanced Functional Decomposition Using Majority and Its Applications.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Zhufei Chu, Mathias Soeken, Yinshui Xia, Lun-Yao Wang, Giovanni De Micheli
2019 — conf
Area Optimization of MPRM Circuits Using Approximate Computing.
ASICON
Qiuhong Ying, Lun-Yao Wang, Zhufei Chu, Yinshui Xia
2019 C conf
Exact Synthesis of Boolean Functions in Majority-of-Five Forms.
ISCAS
Zhufei Chu, Winston Haaswijk, Mathias Soeken, Yinshui Xia, Lun-Yao Wang, Giovanni De Micheli
2019 J jnl
Multi-objective algebraic rewriting in XOR-majority graphs.
Integr.
Zhufei Chu, Lei Shi, Lun-Yao Wang, Yinshui Xia
2019 — conf
Structural rewriting in XOR-majority graphs.
ASP-DAC
Zhufei Chu, Mathias Soeken, Yinshui Xia, Lun-Yao Wang, Giovanni De Micheli
2016 J jnl
Efficient power pad assignment for multi-voltage SoC and its application in floorplanning.
Int. J. Circuit Theory Appl.
Zhufei Chu, Yinshui Xia, Lun-Yao Wang, Jian Wang
2016 J jnl
Multi-supply voltage (MSV) driven SoC floorplanning for fast design convergence.
Integr.
Zhufei Chu, Yinshui Xia, Lun-Yao Wang
2014 J jnl
Efficient nonrectangular shaped voltage island aware floorplanning with nonrandomized searching engine.
Microelectron. J.
Zhufei Chu, Yinshui Xia, Lun-Yao Wang, Jian Wang
2014 — conf
Level shifter planning for timing constrained multi-voltage SoC floorplanning.
ACM Great Lakes Symposium on VLSI
Zhufei Chu, Yinshui Xia, Lun-Yao Wang
2013 — conf
Logic Minimization Based on Dual Logic.
CAD/Graphics
Lun-Yao Wang, Yinshui Xia
2013 J jnl
Low Power State Assignment Algorithm for FSMs Considering Peak Current Optimization.
J. Comput. Sci. Technol.
Lun-Yao Wang, Zhufei Chu, Yinshui Xia
2013 — conf
Voltage Drop Aware Power Pad Assignment and Floorplanning for Multi-voltage SoC Designs.
CAD/Graphics
Zhufei Chu, Yinshui Xia, Lun-Yao Wang, Jian Wang
2012 J jnl
Cell Mapping for Nanohybrid Circuit Architecture Using Genetic Algorithm.
J. Comput. Sci. Technol.
Zhufei Chu, Yinshui Xia, Lun-Yao Wang
2011 J jnl
Reed-Muller function optimization techniques with onset table.
J. Zhejiang Univ. Sci. C
Lun-Yao Wang, Yinshui Xia, Xiexiong Chen, A. E. A. Almaini
2010 C conf
A Memetic Approach for Nanoscale Hybrid Circuit Cell Mapping.
DSD
Zhufei Chu, Yinshui Xia, William N. N. Hung, Lun-Yao Wang, Xiaoyu Song
2005 J jnl
A Novel Multiple-Valued CMOS Flip-Flop Employing Multiple-Valued Clock.
J. Comput. Sci. Technol.
Yinshui Xia, Lun-Yao Wang, A. E. A. Almaini
2005 J jnl
Novel Synthesis and Optimization of Multi-Level Mixed Polarity Reed-Muller Functions.
J. Comput. Sci. Technol.
Yinshui Xia, Lun-Yao Wang, Zong-Gang Zhou, Xien Ye, Jianping Hu
2005 — conf
Novel synthesis method of mixed polarity Reed-Muller functions.
Circuits, Signals, and Systems
Yinshui Xia, Xien Ye, Lun-Yao Wang, Zong-Gang Zhou