Lukás Sekanina

229 papers A* 2A 24B 37C 24Misc 1Journal 53Unranked 77

Year	Rank	Type	Title / Venue / Authors
2025	C	`conf`	Inference Energy Analysis in Context of Hardware-Aware NAS. DDECS Michal Pinos, Jan Klhufek, Vojtech Mrazek, Lukás Sekanina
2025	A	`conf`	Late Breaking Result: FPGA-Based Emulation and Fault Injection for CNN Inference Accelerators. DATE Filip Masar, Vojtech Mrazek, Lukás Sekanina
2025	J	`jnl`	Late Breaking Result: FPGA-Based Emulation and Fault Injection for CNN Inference Accelerators. CoRR Filip Masar, Vojtech Mrazek, Lukás Sekanina
2025	B	`conf`	Multi-objective Evolutionary Design of Explainable EEG Classifier. EuroGP Martin Hurta, Anna Ovesna, Vojtech Mrazek, Lukás Sekanina
2025	J	`jnl`	TransInferSim: Toward Fast and Accurate Evaluation of Embedded Hardware Accelerators for Transformer Networks. IEEE Access Jan Klhufek, Alberto Marchisio, Vojtech Mrazek, Lukás Sekanina, Muhammad Shafique
2024	B	`conf`	ApproxDARTS: Differentiable Neural Architecture Search with Approximate Multipliers. IJCNN Michal Pinos, Lukás Sekanina, Vojtech Mrazek
2024	J	`jnl`	ApproxDARTS: Differentiable Neural Architecture Search with Approximate Multipliers. CoRR Michal Pinos, Lukás Sekanina, Vojtech Mrazek
2024	A	`conf`	Automated Verifiability-Driven Design of Approximate Circuits: Exploiting Error Analysis. DATE Zdenek Vasícek, Vojtech Mrazek, Lukás Sekanina
2024	C	`conf`	Exploring Quantization and Mapping Synergy in Hardware-Aware Deep Neural Network Accelerators. DDECS Jan Klhufek, Miroslav Safar, Vojtech Mrazek, Zdenek Vasícek, Lukás Sekanina
2024	J	`jnl`	Exploring Quantization and Mapping Synergy in Hardware-Aware Deep Neural Network Accelerators. CoRR Jan Klhufek, Miroslav Safar, Vojtech Mrazek, Zdenek Vasícek, Lukás Sekanina
2024	J	`jnl`	Semantic mutation operator for a fast and efficient design of bent Boolean functions. Genet. Program. Evolvable Mach. Jakub Husa, Lukás Sekanina
2024	C	`conf`	Tutorial: Evolutionary Design Methods in Electronic Design Automation. ICCD Lukás Sekanina
2023	A	`conf`	ADEE-LID: Automated Design of Energy-Efficient Hardware Accelerators for Levodopa-Induced Dyskinesia Classifiers. DATE Martin Hurta, Vojtech Mrazek, Michaela Drahosova, Lukás Sekanina
2023	J	`jnl`	Acceleration Techniques for Automated Design of Approximate Convolutional Neural Networks. IEEE J. Emerg. Sel. Topics Circuits Syst. Michal Pinos, Vojtech Mrazek, Filip Vaverka, Zdenek Vasícek, Lukás Sekanina
2023	—	`conf`	Evolution of Editing Scripts From Examples. GECCO Companion Marek Sedlacek, Lukás Sekanina
2023	B	`conf`	GPAM: Genetic Programming with Associative Memory. EuroGP Tadeas Juza, Lukás Sekanina
2023	C	`conf`	MODEE-LID: Multiobjective Design of Energy-Efficient Hardware Accelerators for Levodopa-Induced Dyskinesia Classifiers. DDECS Martin Hurta, Vojtech Mrazek, Michaela Drahosova, Lukás Sekanina
2023	C	`conf`	Prediction of Inference Energy on CNN Accelerators Supporting Approximate Circuits. DDECS Michal Pinos, Vojtech Mrazek, Lukás Sekanina
2023	—	`conf`	Utilizing Genetic Programming to Enhance Polygenic Risk Score Calculation. BIBM Martin Hurta, Jana Schwarzerova, Thomas Nägele, Wolfram Weckwerth, Valentine Provazník, Lukás Sekanina
2023	A	`conf`	Xel-FPGAs: An End-to-End Automated Exploration Framework for Approximate Accelerators in FPGA-Based Systems. ICCAD Bharath Srinivas Prabakaran, Vojtech Mrazek, Zdenek Vasícek, Lukás Sekanina, Muhammad Shafique
2023	J	`jnl`	autoXFPGAs: An End-to-End Automated Exploration Framework for Approximate Accelerators in FPGA-Based Systems. CoRR Bharath Srinivas Prabakaran, Vojtech Mrazek, Zdenek Vasícek, Lukás Sekanina, Muhammad Shafique
2022	B	`conf`	Evolutionary Approximation in Non-Local Means Image Filters. SMC Matej Valek, Lukás Sekanina
2022	B	`conf`	Evolutionary Design of Reduced Precision Levodopa-Induced Dyskinesia Classifiers. EuroGP Martin Hurta, Michaela Drahosova, Lukás Sekanina, Stephen L. Smith, Jane E. Alty
2022	J	`jnl`	Evolutionary approximation and neural architecture search. Genet. Program. Evolvable Mach. Michal Pinos, Vojtech Mrazek, Lukás Sekanina
2022	J	`jnl`	SagTree: Towards efficient mutation in evolutionary circuit approximation. Swarm Evol. Comput. Milan Ceska, Jirí Matyás, Vojtech Mrazek, Lukás Sekanina, Zdenek Vasícek, Tomás Vojnar
2021	C	`ed.`	24th International Symposium on Design and Diagnostics of Electronic Circuits & Systems, DDECS 2021, Vienna, Austria, April 7-9, 2021 DDECS Muhammad Shafique, Andreas Steininger, Lukás Sekanina, Milos Krstic, Goran Stojanovic, Vojtech Mrazek
2021	J	`jnl`	Editorial: Special issue on Advancing on Approximate Computing: Methodologies, Architectures and Algorithms. Future Gener. Comput. Syst. Mario Barbareschi, Alberto Bosio, Lukás Sekanina, Claus Braun
2021	J	`jnl`	Evolutionary Algorithms in Approximate Computing: A Survey. CoRR Lukás Sekanina
2021	B	`conf`	Evolutionary Neural Architecture Search Supporting Approximate Multipliers. EuroGP Michal Pinos, Vojtech Mrazek, Lukás Sekanina
2021	J	`jnl`	Evolutionary Neural Architecture Search Supporting Approximate Multipliers. CoRR Michal Pinos, Vojtech Mrazek, Lukás Sekanina
2021	J	`jnl`	Neural Architecture Search and Hardware Accelerator Co-Search: A Survey. IEEE Access Lukás Sekanina
2020	J	`jnl`	Adaptive Verifiability-Driven Strategy for Evolutionary Approximation of Arithmetic Circuits. CoRR Milan Ceska, Jirí Matyás, Vojtech Mrazek, Lukás Sekanina, Zdenek Vasícek, Tomás Vojnar
2020	J	`jnl`	Adaptive verifiability-driven strategy for evolutionary approximation of arithmetic circuits. Appl. Soft Comput. Milan Ceska, Jirí Matyás, Vojtech Mrazek, Lukás Sekanina, Zdenek Vasícek, Tomás Vojnar
2020	A*	`conf`	ApproxFPGAs: Embracing ASIC-Based Approximate Arithmetic Components for FPGA-Based Systems. DAC Bharath Srinivas Prabakaran, Vojtech Mrazek, Zdenek Vasícek, Lukás Sekanina, Muhammad Shafique
2020	J	`jnl`	ApproxFPGAs: Embracing ASIC-Based Approximate Arithmetic Components for FPGA-Based Systems. CoRR Bharath Srinivas Prabakaran, Vojtech Mrazek, Zdenek Vasícek, Lukás Sekanina, Muhammad Shafique
2020	B	`conf`	Design, Verification, Test and In-Field Implications of Approximate Computing Systems. ETS Alberto Bosio, Stefano Di Carlo, Patrick Girard, Ernesto Sánchez, Alessandro Savino, Lukás Sekanina, Marcello Traiola, Zdenek Vasícek, Arnaud Virazel
2020	B	`conf`	Evolutionary Design of Hash Functions for IPv6 Network Flow Hashing. CEC David Grochol, Lukás Sekanina
2020	B	`conf`	Evolving Cryptographic Boolean Functions with Minimal Multiplicative Complexity. CEC Jakub Husa, Lukás Sekanina
2020	J	`jnl`	Improving the Accuracy and Hardware Efficiency of Neural Networks Using Approximate Multipliers. IEEE Trans. Very Large Scale Integr. Syst. Mohammad Saeed Ansari, Vojtech Mrazek, Bruce F. Cockburn, Lukás Sekanina, Zdenek Vasícek, Jie Han
2020	J	`jnl`	Libraries of Approximate Circuits: Automated Design and Application in CNN Accelerators. IEEE J. Emerg. Sel. Topics Circuits Syst. Vojtech Mrazek, Lukás Sekanina, Zdenek Vasícek
2020	J	`jnl`	Special issue on highlights of genetic programming 2019 events. Genet. Program. Evolvable Mach. Ting Hu, Miguel Nicolau, Lukás Sekanina
2020	A	`conf`	TFApprox: Towards a Fast Emulation of DNN Approximate Hardware Accelerators on GPU. DATE Filip Vaverka, Vojtech Mrazek, Zdenek Vasícek, Lukás Sekanina
2020	J	`jnl`	TFApprox: Towards a Fast Emulation of DNN Approximate Hardware Accelerators on GPU. CoRR Filip Vaverka, Vojtech Mrazek, Zdenek Vasícek, Lukás Sekanina
2020	—	`conf`	Using Libraries of Approximate Circuits in Design of Hardware Accelerators of Deep Neural Networks. AICAS Vojtech Mrazek, Lukás Sekanina, Zdenek Vasícek
2020	J	`jnl`	Using Libraries of Approximate Circuits in Design of Hardware Accelerators of Deep Neural Networks. CoRR Vojtech Mrazek, Lukás Sekanina, Zdenek Vasícek
2019	A	`conf`	ALWANN: Automatic Layer-Wise Approximation of Deep Neural Network Accelerators without Retraining. ICCAD Vojtech Mrazek, Zdenek Vasícek, Lukás Sekanina, Muhammad Abdullah Hanif, Muhammad Shafique
2019	J	`jnl`	ALWANN: Automatic Layer-Wise Approximation of Deep Neural Network Accelerators without Retraining. CoRR Vojtech Mrazek, Zdenek Vasícek, Lukás Sekanina, Muhammad Abdullah Hanif, Muhammad Shafique
2019	J	`jnl`	Adaptive Fitness Predictors in Coevolutionary Cartesian Genetic Programming. Evol. Comput. Michaela Drahosova, Lukás Sekanina, Michal Wiglasz
2019	A	`conf`	Automated Circuit Approximation Method Driven by Data Distribution. DATE Zdenek Vasícek, Vojtech Mrazek, Lukás Sekanina
2019	J	`jnl`	Automated Circuit Approximation Method Driven by Data Distribution. CoRR Zdenek Vasícek, Vojtech Mrazek, Lukás Sekanina
2019	—	`ch.`	Automated Search-Based Functional Approximation for Digital Circuits. Approximate Circuits Lukás Sekanina, Zdenek Vasícek, Vojtech Mrazek
2019	B	`conf`	Cartesian Genetic Programming as an Optimizer of Programs Evolved with Geometric Semantic Genetic Programming. EuroGP Ondrej Koncal, Lukás Sekanina
2019	J	`jnl`	Efficient On-Chip Randomness Testing Utilizing Machine Learning Techniques. IEEE Trans. Very Large Scale Integr. Syst. Vojtech Mrazek, Lukás Sekanina, Roland Dobai, Marek Sýs, Petr Svenda
2019	B	`ed.`	Genetic Programming - 22nd European Conference, EuroGP 2019, Held as Part of EvoStar 2019, Leipzig, Germany, April 24-26, 2019, Proceedings EuroGP Lukás Sekanina, Ting Hu, Nuno Lourenço, Hendrik Richter, Pablo García-Sánchez
2019	A	`conf`	International Symposium on Design and Diagnostics of Electronic Circuits and Systems. ITC Zoran Stamenkovic, Alberto Bosio, György Cserey, Ondrej Novák, Witold A. Pleskacz, Lukás Sekanina, Andreas Steininger, Goran Stojanovic, Viera Stopjaková
2019	—	`conf`	Optimizing Convolutional Neural Networks for Embedded Systems by Means of Neuroevolution. TPNC Filip Badan, Lukás Sekanina
2019	J	`jnl`	Optimizing Convolutional Neural Networks for Embedded Systems by Means of Neuroevolution. CoRR Filip Badan, Lukás Sekanina
2019	A	`conf`	TypeCNN: CNN Development Framework With Flexible Data Types. DATE Petr Rek, Lukás Sekanina
2019	A*	`conf`	autoAx: An Automatic Design Space Exploration and Circuit Building Methodology utilizing Libraries of Approximate Components. DAC Vojtech Mrazek, Muhammad Abdullah Hanif, Zdenek Vasícek, Lukás Sekanina, Muhammad Shafique
2019	J	`jnl`	autoAx: An Automatic Design Space Exploration and Circuit Building Methodology utilizing Libraries of Approximate Components. CoRR Vojtech Mrazek, Muhammad Abdullah Hanif, Zdenek Vasícek, Lukás Sekanina, Muhammad Shafique
2018	—	`conf`	ADAC: Automated Design of Approximate Circuits. CAV (1) Milan Ceska, Jirí Matyás, Vojtech Mrazek, Lukás Sekanina, Zdenek Vasícek, Tomás Vojnar
2018	—	`conf`	Cooperative Coevolutionary Approximation in HOG-based Human Detection Embedded System. SSCI Michal Wiglasz, Lukás Sekanina
2018	—	`conf`	Design Space Exploration for Approximate Implementations of Arithmetic Data Path Primitives. ICECS Lukás Sekanina, Vojtech Mrazek, Zdenek Vasícek
2018	—	`conf`	Design of Quality-Configurable Approximate Multipliers Suitable for Dynamic Environment. AHS Vojtech Mrazek, Zdenek Vasícek, Lukás Sekanina
2018	A	`conf`	Evolving boolean functions for fast and efficient randomness testing. GECCO Vojtech Mrazek, Marek Sýs, Zdenek Vasícek, Lukás Sekanina, Vashek Matyas
2018	—	`conf`	Fast Reconfigurable Hash Functions for Network Flow Hashing in FPGAs. AHS David Grochol, Lukás Sekanina
2018	B	`ed.`	Genetic Programming - 21st European Conference, EuroGP 2018, Parma, Italy, April 4-6, 2018, Proceedings EuroGP Mauro Castelli, Lukás Sekanina, Mengjie Zhang, Stefano Cagnoni, Pablo García-Sánchez
2018	B	`conf`	Multi-objective Evolution of Ultra-Fast General-Purpose Hash Functions. EuroGP David Grochol, Lukás Sekanina
2018	J	`jnl`	Scalable Construction of Approximate Multipliers With Formally Guaranteed Worst Case Error. IEEE Trans. Very Large Scale Integr. Syst. Vojtech Mrazek, Zdenek Vasícek, Lukás Sekanina, Honglan Jiang, Jie Han
2018	Misc	`conf`	Special session: How approximate computing impacts verification, test and reliability. VTS Lukás Sekanina, Zdenek Vasícek, Alberto Bosio, Marcello Traiola, Paolo Rech, Daniel Oliveira, Fernando Fernandes, Stefano Di Carlo
2017	—	`conf`	Adaptive and Energy-Efficient Architectures for Machine Learning: Challenges, Opportunities, and Research Roadmap. ISVLSI Muhammad Shafique, Rehan Hafiz, Muhammad Usama Javed, Sarmad Abbas, Lukás Sekanina, Zdenek Vasícek, Vojtech Mrazek
2017	A	`conf`	Approximating complex arithmetic circuits with formal error guarantees: 32-bit multipliers accomplished. ICCAD Milan Ceska, Jirí Matyás, Vojtech Mrazek, Lukás Sekanina, Zdenek Vasícek, Tomás Vojnar
2017	A	`conf`	EvoApproxSb: Library of approximate adders and multipliers for circuit design and benchmarking of approximation methods. DATE Vojtech Mrazek, Radek Hrbacek, Zdenek Vasícek, Lukás Sekanina
2017	—	`conf`	Evolutionary approximation of gradient orientation module in HOG-based human detection system. GlobalSIP Michal Wiglasz, Lukás Sekanina
2017	J	`jnl`	Evolutionary design of hash function pairs for network filters. Appl. Soft Comput. Roland Dobai, Jan Korenek, Lukás Sekanina
2017	B	`ed.`	Genetic Programming - 20th European Conference, EuroGP 2017, Amsterdam, The Netherlands, April 19-21, 2017, Proceedings EuroGP James McDermott, Mauro Castelli, Lukás Sekanina, Evert Haasdijk, Pablo García-Sánchez
2017	—	`conf`	Modular framework for detection of inter-ictal spikes in iEEG. EMBC Filip Kesner, Lukás Sekanina, Milan Brazdil
2017	B	`conf`	Multi-objective evolution of hash functions for high speed networks. CEC David Grochol, Lukás Sekanina
2017	B	`conf`	On Evolutionary Approximation of Sigmoid Function for HW/SW Embedded Systems. EuroGP Milos Minarik, Lukás Sekanina
2017	A	`conf`	Towards low power approximate DCT architecture for HEVC standard. DATE Zdenek Vasícek, Vojtech Mrazek, Lukás Sekanina
2016	—	`conf`	Adaptive development of hash functions in FPGA-based network routers. SSCI Roland Dobai, Jan Korenek, Lukás Sekanina
2016	A	`conf`	Design of power-efficient approximate multipliers for approximate artificial neural networks. ICCAD Vojtech Mrazek, Syed Shakib Sarwar, Lukás Sekanina, Zdenek Vasícek, Kaushik Roy
2016	J	`jnl`	Error Mitigation Using Approximate Logic Circuits: A Comparison of Probabilistic and Evolutionary Approaches. IEEE Trans. Reliab. Antonio Sanchez-Clemente, Luis Entrena, Radek Hrbacek, Lukás Sekanina
2016	B	`conf`	Evolutionary Approximation of Edge Detection Circuits. EuroGP Petr Dvoracek, Lukás Sekanina
2016	A	`conf`	Evolutionary Design of Fast High-quality Hash Functions for Network Applications. GECCO David Grochol, Lukás Sekanina
2016	J	`jnl`	Evolutionary circuit design for fast FPGA-based classification of network application protocols. Appl. Soft Comput. David Grochol, Lukás Sekanina, Martin Zádník, Jan Korenek, Vlastimil Kosar
2016	J	`jnl`	Evolutionary design of complex approximate combinational circuits. Genet. Program. Evolvable Mach. Zdenek Vasícek, Lukás Sekanina
2016	—	`conf`	Evolutionary functional approximation of circuits implemented into FPGAs. SSCI Zdenek Vasícek, Vojtech Mrazek, Lukás Sekanina
2016	—	`conf`	Evolving component library for approximate high level synthesis. SSCI Filip Vaverka, Radek Hrbacek, Lukás Sekanina
2016	C	`conf`	Introduction to approximate computing: Embedded tutorial. DDECS Lukás Sekanina
2016	B	`conf`	Search-based synthesis of approximate circuits implemented into FPGAs. FPL Zdenek Vasícek, Lukás Sekanina
2016	—	`conf`	Visualisation and Analysis of Genetic Records Produced by Cartesian Genetic Programming. GECCO (Companion) Lukás Sekanina, Vlastimil Kapusta
2015	B	`conf`	A Fast FPGA-Based Classification of Application Protocols Optimized Using Cartesian GP. EvoApplications David Grochol, Lukás Sekanina, Martin Zádník, Jan Korenek
2015	B	`conf`	Circuit Approximation Using Single- and Multi-objective Cartesian GP. EuroGP Zdenek Vasícek, Lukás Sekanina
2015	J	`jnl`	Evolutionary Approach to Approximate Digital Circuits Design. IEEE Trans. Evol. Comput. Zdenek Vasícek, Lukás Sekanina
2015	—	`conf`	Evolutionary Approximation of Complex Digital Circuits. GECCO (Companion) Zdenek Vasícek, Lukás Sekanina
2015	—	`conf`	Evolutionary Approximation of Software for Embedded Systems: Median Function. GECCO (Companion) Vojtech Mrazek, Zdenek Vasícek, Lukás Sekanina
2015	—	`ch.`	Functional Equivalence Checking for Evolution of Complex Digital Circuits. Evolvable Hardware Lukás Sekanina, Zdenek Vasícek
2015	B	`conf`	Indirectly Encoded Fitness Predictors Coevolved with Cartesian Programs. EuroGP Michaela Sikulová, Jiri Hulva, Lukás Sekanina
2015	J	`jnl`	Low-Level Flexible Architecture with Hybrid Reconfiguration for Evolvable Hardware. ACM Trans. Reconfigurable Technol. Syst. Roland Dobai, Lukás Sekanina
2015	—	`ch.`	Principles and Applications of Polymorphic Circuits. Evolvable Hardware Lukás Sekanina
2015	—	`conf`	Towards Robust and Accurate Traffic Prediction Using Parallel Multiobjective Genetic Algorithms and Support Vector Regression. ITSC Jiri Petrlik, Lukás Sekanina
2014	B	`conf`	Cartesian genetic programming as local optimizer of logic networks. IEEE Congress on Evolutionary Computation Lukás Sekanina, Ondrej Ptak, Zdenek Vasícek
2014	C	`conf`	Evolutionary design of approximate multipliers under different error metrics. DDECS Zdenek Vasícek, Lukás Sekanina
2014	—	`conf`	Evolutionary digital circuit design with fast candidate solution establishment in field programmable gate arrays. ICES Roland Dobai, Kyrre Glette, Jim Tørresen, Lukás Sekanina
2014	B	`conf`	Exploring the Search Space of Hardware / Software Embedded Systems by Means of GP. EuroGP Milos Minarik, Lukás Sekanina
2014	—	`conf`	How to evolve complex combinational circuits from scratch? ICES Zdenek Vasícek, Lukás Sekanina
2014	A	`conf`	Multiobjective Selection of Input Sensors for SVR Applied to Road Traffic Prediction. PPSN Jiri Petrlik, Otto Fucík, Lukás Sekanina
2014	—	`conf`	Multiobjective selection of input sensors for travel times forecasting using support vector regression. CIVTS Jiri Petrlik, Otto Fucík, Lukás Sekanina
2014	—	`conf`	On Evolutionary Approximation of Logic Circuits. Computing with New Resources Lukás Sekanina, Zdenek Vasícek
2014	—	`conf`	Towards compositional coevolution in evolutionary circuit design. ICES Michaela Sikulová, Gergely Komjathy, Lukás Sekanina
2014	A	`conf`	Towards highly optimized cartesian genetic programming: from sequential via SIMD and thread to massive parallel implementation. GECCO Radek Hrbacek, Lukás Sekanina
2013	C	`ed.`	16th IEEE International Symposium on Design and Diagnostics of Electronic Circuits & Systems, DDECS 2013, Karlovy Vary, Czech Republic, April 8-10, 2013 DDECS Lukás Sekanina, Görschwin Fey, Jaan Raik, Snorre Aunet, Richard Ruzicka
2013	J	`jnl`	Advanced Approach to Calibration of Traffic Microsimulation Models Using Travel Times. J. Cell. Autom. Pavol Korcek, Lukás Sekanina, Otto Fucík
2013	—	`conf`	Approximate circuit design by means of evolvable hardware. ICES Lukás Sekanina, Zdenek Vasícek
2013	—	`conf`	Concurrent evolution of hardware and software for application-specific microprogrammed systems. ICES Milos Minarik, Lukás Sekanina
2013	J	`jnl`	Evolution of efficient real-time non-linear image filters for FPGAs. Soft Comput. Zdenek Vasícek, Michal Bidlo, Lukás Sekanina
2013	—	`conf`	Image filter evolution on the Xilinx Zynq Platform. AHS Roland Dobai, Lukás Sekanina
2013	J	`jnl`	Implementing A Unique Chip Id On A Reconfigurable Polymorphic Circuit. Inf. Technol. Control. Lukás Sekanina, Richard Ruzicka, Zdenek Vasícek, Václav Simek, Petr Hanácek
2013	C	`conf`	Multiobjective evolution of approximate multiple constant multipliers. DDECS Jiri Petrlik, Lukás Sekanina
2013	J	`jnl`	Self-Reconfigurable Evolvable Hardware System for Adaptive Image Processing. IEEE Trans. Computers Rubén Salvador, Andrés Otero, Javier Mora, Eduardo de la Torre, Teresa Riesgo, Lukás Sekanina
2013	—	`conf`	Towards evolvable systems based on the Xilinx Zynq platform. ICES Roland Dobai, Lukás Sekanina
2013	J	`jnl`	Ubiquity symposium: Evolutionary computation and the processes of life: evolutionary computation in physical world. Ubiquity Lukás Sekanina
2012	A	`conf`	A SAT-based fitness function for evolutionary optimization of polymorphic circuits. DATE Lukás Sekanina, Zdenek Vasícek
2012	J	`jnl`	Accelerating FPGA-based evolution of wavelet transform filters by optimized task scheduling. Microprocess. Microsystems Rubén Salvador, Alberto Vidal, Félix Moreno, Teresa Riesgo, Lukás Sekanina
2012	—	`conf`	Acceleration of Evolutionary Image Filter Design Using Coevolution in Cartesian GP. PPSN (1) Michaela Sikulová, Lukás Sekanina
2012	—	`conf`	Calibration of Traffic Simulation Models Using Vehicle Travel Times. ACRI Pavol Korcek, Lukás Sekanina, Otto Fucík
2012	J	`jnl`	Cellular automata-based systems with fault-tolerance. Nat. Comput. Ludek Zaloudek, Lukás Sekanina
2012	B	`conf`	Coevolution in Cartesian Genetic Programming. EuroGP Michaela Sikulová, Lukás Sekanina
2012	—	`conf`	Estimation of missing values in traffic density maps. ITSC Jiri Petrlik, Pavol Korcek, Otto Fucík, Marian Beszédes, Lukás Sekanina
2012	B	`conf`	Evolutionary Design of Message Efficient Secrecy Amplification Protocols. EuroGP Tobiás Smolka, Petr Svenda, Lukás Sekanina, Vashek Matyás
2012	—	`conf`	Evolutionary approach to calibration of cellular automaton based traffic simulation models. ITSC Pavol Korcek, Lukás Sekanina, Otto Fucík
2012	—	`ch.`	Evolvable Hardware. Handbook of Natural Computing Lukás Sekanina
2012	B	`conf`	Implementation techniques for evolvable HW systems: virtual VS. dynamic reconfiguration. FPL Rubén Salvador, Andrés Otero, Javier Mora, Eduardo de la Torre, Teresa Riesgo, Lukás Sekanina
2012	—	`ed.`	Mathematical and Engineering Methods in Computer Science - 7th International Doctoral Workshop, MEMICS 2011, Lednice, Czech Republic, October 14-16, 2011, Revised Selected Papers MEMICS Zdenek Kotásek, Jan Bouda, Ivana Cerná, Lukás Sekanina, Tomás Vojnar, David Antos
2012	B	`conf`	On area minimization of complex combinational circuits using cartesian genetic programming. IEEE Congress on Evolutionary Computation Zdenek Vasícek, Lukás Sekanina
2012	A	`conf`	Towards new applications of multi-function logic: Image multi-filtering. DATE Lukás Sekanina, Vojtech Salajka
2012	B	`conf`	Two-step evolution of polymorphic circuits for image multi-filtering. IEEE Congress on Evolutionary Computation Lukás Sekanina, Vojtech Salajka, Zdenek Vasícek
2012	J	`jnl`	pecial CAI Section Devoted to MEMICS '11: Preface. Comput. Informatics Zdenek Kotásek, Lukás Sekanina, Tomás Vojnar, Jan Bouda, Ivana Cerná
2011	—	`conf`	A fast Reconfigurable 2D HW core architecture on FPGAs for evolvable Self-Adaptive Systems. AHS Andrés Otero, Rubén Salvador, Javier Mora, Eduardo de la Torre, Teresa Riesgo, Lukás Sekanina
2011	A	`conf`	A global postsynthesis optimization method for combinational circuits. DATE Zdenek Vasícek, Lukás Sekanina
2011	B	`conf`	A scalable cellular automata based microscopic traffic simulation. Intelligent Vehicles Symposium Pavol Korcek, Lukás Sekanina, Otto Fucík
2011	C	`conf`	Behavior of CMOS polymorphic circuits in high temperature environment. DDECS Richard Ruzicka, Václav Simek, Lukás Sekanina
2011	—	`ch.`	CGP Acceleration Using Field-Programmable Gate Arrays. Cartesian Genetic Programming Lukás Sekanina, Zdenek Vasícek
2011	—	`ch.`	Evolution of Electronic Circuits. Cartesian Genetic Programming Lukás Sekanina, James Alfred Walker, Paul Kaufmann, Marco Platzner
2011	—	`conf`	Evolution of Iterative Formulas Using Cartesian Genetic Programming. KES (1) Milos Minarik, Lukás Sekanina
2011	—	`conf`	Evolution of digital circuits. GECCO (Companion) Lukás Sekanina
2011	J	`jnl`	Evolutionary Approach to Improve Wavelet Transforms for Image Compression in Embedded Systems. EURASIP J. Adv. Signal Process. Rubén Salvador, Félix Moreno, Teresa Riesgo, Lukás Sekanina
2011	—	`conf`	Evolutionary design of efficient and robust switching image filters. AHS Zdenek Vasícek, Michal Bidlo, Lukás Sekanina, Kyrre Glette
2011	—	`conf`	Evolvable 2D computing matrix model for intrinsic evolution in commercial FPGAs with native reconfiguration support. AHS Rubén Salvador, Andrés Otero, Javier Mora, Eduardo de la Torre, Teresa Riesgo, Lukás Sekanina
2011	—	`conf`	Fault Tolerance Analysis and Self-Healing Strategy of Autonomous, Evolvable Hardware Systems. ReConFig Rubén Salvador, Andrés Otero, Javier Mora, Eduardo de la Torre, Lukás Sekanina, Teresa Riesgo
2011	J	`jnl`	Formal verification of candidate solutions for post-synthesis evolutionary optimization in evolvable hardware. Genet. Program. Evolvable Mach. Zdenek Vasícek, Lukás Sekanina
2011	J	`jnl`	Global Control in Polymorphic Cellular Automata. J. Cell. Autom. Lukás Sekanina, Tomas Komenda
2011	—	`ch.`	Image Processing and CGP. Cartesian Genetic Programming Lukás Sekanina, Simon L. Harding, Wolfgang Banzhaf, Taras Kowaliw
2011	C	`conf`	Increasing Fault-Tolerance in Cellular Automata-Based Systems. UC Ludek Zaloudek, Lukás Sekanina
2011	J	`jnl`	On Evolutionary Synthesis of Compact Polymorphic Combinational Circuits. J. Multiple Valued Log. Soft Comput. Zbysek Gajda, Lukás Sekanina
2010	A	`conf`	A method for design of impulse bursts noise filters optimized for FPGA implementations. DATE Zdenek Vasícek, Lukás Sekanina, Michal Bidlo
2010	—	`conf`	An Efficient Selection Strategy for Digital Circuit Evolution. ICES Zbysek Gajda, Lukás Sekanina
2010	—	`conf`	Evolutionary Design of Reconfiguration Strategies to Reduce the Test Application Time. ICES Jirí Simácek, Lukás Sekanina, Lukás Starecek
2010	C	`conf`	Evolutionary circuit design: Tutorial. DDECS Lukás Sekanina
2010	—	`conf`	Evolutionary design and optimization of Wavelet Transforms for image compression in embedded systems. AHS Rubén Salvador, Félix Moreno, Teresa Riesgo, Lukás Sekanina
2010	C	`conf`	High Level Validation of an Optimization Algorithm for the Implementation of Adaptive Wavelet Transforms in FPGAs. DSD Rubén Salvador, Félix Moreno, Teresa Riesgo, Lukás Sekanina
2010	C	`conf`	On analysis of fabricated polymorphic circuits. DDECS Václav Simek, Richard Ruzicka, Lukás Sekanina
2010	C	`conf`	On logic synthesis of conventionally hard to synthesize circuits using genetic programming. DDECS Petr Fiser, Jan Schmidt, Zdenek Vasícek, Lukás Sekanina
2010	A	`conf`	When does Cartesian genetic programming minimize the phenotype size implicitly? GECCO Zbysek Gajda, Lukás Sekanina
2009	—	`conf`	Evolution of Impulse Bursts Noise Filters. AHS Zdenek Vasícek, Michal Bidlo, Lukás Sekanina, Jim Tørresen, Kyrre Glette, Marcus Furuholmen
2009	—	`conf`	Evolutionary design of secrecy amplification protocols for wireless sensor networks. WISEC Petr Svenda, Lukás Sekanina, Václav Matyás
2009	C	`conf`	Evolvable Hardware: From Applications to Implications for the Theory of Computation. UC Lukás Sekanina
2009	B	`conf`	Gate-level optimization of polymorphic circuits using Cartesian Genetic Programming. IEEE Congress on Evolutionary Computation Zbysek Gajda, Lukás Sekanina
2009	—	`conf`	Polymorphic FIR Filters with Backup Mode Enabling Power Savings. AHS Lukás Sekanina, Richard Ruzicka, Zbysek Gajda
2009	—	`conf`	REPOMO32 - New reconfigurable polymorphic integrated circuit for adaptive hardware. WEAH Lukás Sekanina, Richard Ruzicka, Zdenek Vasícek, Roman Prokop, Lukás Fujcik
2008	—	`conf`	Adaptive and Evolvable Hardware and Systems: The State of the Art and the Prospectus for Future Development. KES (3) Mircea Gh. Negoita, Lukás Sekanina, Adrian Stoica
2008	—	`conf`	Analysis of Reconfigurable Logic Blocks for Evolvable Digital Architectures. EvoWorkshops Lukás Sekanina, Petr Mikusek
2008	—	`conf`	Analysis of Reconfiguration Options for a Reconfigurable Polymorphic Circuit. AHS Zdenek Vasícek, Ladislav Capka, Lukás Sekanina
2008	J	`jnl`	Evolution of synthetic RTL benchmark circuits with predefined testability. ACM Trans. Design Autom. Electr. Syst. Tomas Pecenka, Lukás Sekanina, Zdenek Kotásek
2008	—	`ed.`	Evolvable Systems: From Biology to Hardware, 8th International Conference, ICES 2008, Prague, Czech Republic, September 21-24, 2008. Proceedings ICES Gregory Hornby, Lukás Sekanina, Pauline C. Haddow
2008	B	`conf`	Hardware Accelerators for Cartesian Genetic Programming. EuroGP Zdenek Vasícek, Lukás Sekanina
2008	C	`conf`	Novel Hardware Implementation of Adaptive Median Filters. DDECS Zdenek Vasícek, Lukás Sekanina
2008	—	`conf`	On Evolutionary Synthesis of Linear Transforms in FPGA. ICES Zdenek Vasícek, Martin Zádník, Lukás Sekanina, Jirí Tobola
2008	C	`conf`	Physical Demonstration of Polymorphic Self-Checking Circuits. IOLTS Richard Ruzicka, Lukás Sekanina, Roman Prokop
2008	J	`jnl`	Polymorphic Gates in Design and Test of Digital Circuits. Int. J. Unconv. Comput. Lukás Sekanina, Lukás Starecek, Zdenek Kotásek, Zbysek Gajda
2008	C	`conf`	Reduction of Test Vectors Volume by Means of Gate-Level Reconfiguration. DDECS Lukás Starecek, Lukás Sekanina, Zdenek Kotásek
2008	—	`conf`	Transistor-Level Evolution of Digital Circuits Using a Special Circuit Simulator. ICES Ludek Zaloudek, Lukás Sekanina
2007	B	`conf`	An area-efficient alternative to adaptive median filtering in FPGAs. FPL Zdenek Vasícek, Lukás Sekanina
2007	C	`conf`	Design and Analysis of a New Self-Testing Adder which Utilizes Polymorphic Gates. DDECS Lukás Sekanina
2007	—	`conf`	Evaluation of a New Platform For Image Filter Evolution. AHS Zdenek Vasícek, Lukás Sekanina
2007	—	`conf`	Evolution of Polymorphic Self-checking Circuits. ICES Lukás Sekanina
2007	J	`jnl`	Evolutionary functional recovery in virtual reconfigurable circuits. ACM J. Emerg. Technol. Comput. Syst. Lukás Sekanina
2007	—	`conf`	Evolvable hardware. GECCO (Companion) Lukás Sekanina
2007	J	`jnl`	Evolved Computing Devices and the Implementation Problem. Minds Mach. Lukás Sekanina
2007	B	`conf`	Fitness Landscape Analysis and Image Filter Evolution Using Functional-Level CGP. EuroGP Karel Slaný, Lukás Sekanina
2007	—	`conf`	On Some Directions in Security-Oriented Research. BLISS Lukás Sekanina, Tomas Hruska, Tomás Vojnar, Dusan Kolár, Jan Cernocký
2007	—	`conf`	Reducing the Area on a Chip Using a Bank of Evolved Filters. ICES Zdenek Vasícek, Lukás Sekanina
2007	A	`conf`	Reducing the number of transistors in digital circuits using gate-level evolutionary design. GECCO Zbysek Gajda, Lukás Sekanina
2006	—	`ch.`	Characterization and Synthesis of Circuits at Extreme Low Temperatures. Evolvable Hardware Ricardo Salem Zebulum, Didier Keymeulen, Rajeshuni Ramesham, Lukás Sekanina, James Mao, Nikhil Kumar, Adrian Stoica
2006	—	`conf`	Evolution of Multifunctional Combinational Modules Controlled by the Power Supply Voltage. AHS Lukás Sekanina, Lukás Starecek, Zbysek Gajda, Zdenek Kotásek
2006	—	`conf`	Evolutionary Design of Digital Circuits: Where Are Current Limits? AHS Lukás Sekanina
2006	—	`conf`	Evolutionary circuit design in REPOMO - reconfigurable polymorphic module. Computational Intelligence Richard Ruzicka, Lukás Sekanina
2006	B	`conf`	Extrinsic and Intrinsic Evolution of Multifunctional Combinational Modules. IEEE Congress on Evolutionary Computation Lukás Sekanina, Tomás Martínek, Zbysek Gajda
2006	C	`conf`	FITTest_BENCH06: A New Set of Benchmark Circuits Reflecting Diagnostic Properties. DDECS Tomas Pecenka, Zdenek Kotásek, Lukás Sekanina
2006	C	`conf`	Novel Logic Circuits Controlled by Vdd: Transistor-Level Simulations of Polymorphic Combinational Modules. DDECS Lukás Sekanina, Lukás Starecek, Zdenek Kotásek
2006	—	`conf`	On dependability of FPGA-based evolvable hardware systems that utilize virtual reconfigurable circuits. Conf. Computing Frontiers Lukás Sekanina
2006	—	`conf`	On the Practical Limits of the Evolutionary Digital Filter Design at the Gate Level. EvoWorkshops Lukás Sekanina, Zdenek Vasícek
2006	C	`conf`	Testability Estimation Based on Controllability and Observability Parameters. DSD Tomas Pecenka, Josef Strnadel, Zdenek Kotásek, Lukás Sekanina
2005	—	`conf`	An Evolvable Image Filter: Experimental Evaluation of a Complete Hardware Implementation in FPGA. ICES Tomás Martínek, Lukás Sekanina
2005	—	`conf`	Automatic Discovery of RTL Benchmark Circuits with Predefined Testability Properties. Evolvable Hardware Tomas Pecenka, Zdenek Kotásek, Lukás Sekanina, Josef Strnadel
2005	J	`jnl`	Evolutionary Design of Arbitrarily Large Sorting Networks Using Development. Genet. Program. Evolvable Mach. Lukás Sekanina, Michal Bidlo
2005	—	`conf`	Evolutionary Design of Gate-Level Polymorphic Digital Circuits. EvoWorkshops Lukás Sekanina
2005	—	`conf`	Evolutionary Discovering of the Concept of the Discrete State at the Transistor Level. Evolvable Hardware Lukás Sekanina, Ricardo Salem Zebulum
2005	J	`jnl`	Evolvable Components-From Theory to Hardware Implementations. Genet. Program. Evolvable Mach. Lukás Sekanina, Tughrul Arslan
2005	—	`conf`	Evolvable Hardware System at Extreme Low Temperatures. ICES Ricardo Salem Zebulum, Adrian Stoica, Didier Keymeulen, Lukás Sekanina, Rajeshuni Ramesham, Xin Guo
2005	—	`conf`	Intrinsic Evolution of Controllable Oscillators in FPTA-2. ICES Lukás Sekanina, Ricardo Salem Zebulum
2005	—	`conf`	Intrinsic Evolution of Sorting Networks: A Novel Complete Hardware Implementation for FPGAs. ICES Jan Korenek, Lukás Sekanina
2005	—	`conf`	Providing information from the environment for growing electronic circuits through polymorphic gates. GECCO Workshops Michal Bidlo, Lukás Sekanina
2004	J	`jnl`	An Evolvable Combinational Unit for FPGAs. Comput. Artif. Intell. Lukás Sekanina, Stepan Friedl
2004	—	`conf`	Evolutionary Design Space Exploration for Median Circuits. EvoWorkshops Lukás Sekanina
2004	—	`book`	Evolvable components - from theory to hardware implementations. Lukás Sekanina
2004	B	`conf`	Evolving Constructors for Infinitely Growing Sorting Networks and Medians. SOFSEM Lukás Sekanina
2004	—	`conf`	On Routine Implementation of Virtual Evolvable Devices Using COMBO6. Evolvable Hardware Lukás Sekanina, Stepan Friedl
2004	A	`conf`	Recognizing Speed Limit Sign Numbers by Evolvable Hardware. PPSN Jim Tørresen, Jorgen W. Bakke, Lukás Sekanina
2004	—	`conf`	Theory and Applications of Evolvable Embedded Systems. ECBS Lukás Sekanina, Vladimír Drábek
2003	—	`conf`	Easily Testable Image Operators: The Class of Circuits Where Evolution Beats Engineers. Evolvable Hardware Lukás Sekanina, Richard Ruzicka
2003	B	`conf`	From Implementations to a General Concept of Evolvable Machines. EuroGP Lukás Sekanina
2003	—	`conf`	Towards Evolvable IP Cores for FPGAs. Evolvable Hardware Lukás Sekanina
2003	—	`conf`	Virtual Reconfigurable Circuits for Real-World Applications of Evolvable Hardware. ICES Lukás Sekanina
2002	—	`conf`	Detection of Norwegian Speed Limit Signs. ESM Lukás Sekanina, Jim Tørresen
2002	—	`conf`	Image Filter Design with Evolvable Hardware. EvoWorkshops Lukás Sekanina
2000	—	`conf`	Relation between Fault Tolerance and Reconfiguration in Cellular Systems. IOLTW Lukás Sekanina, Vladimír Drábek
2000	B	`conf`	Toward Uniform Approach to Design of Evolvable Hardware Based Systems. FPL Lukás Sekanina, Azeddien M. Sllame