Lukas Kekely

14 papers A* 1A 2B 4C 5Journal 1Unranked 1
YearRankTypeTitle / Venue / Authors
2018 B conf
Accelerated Wire-Speed Packet Capture at 200 Gbps.
FPL
Lukas Kekely, Martin Spinler, Stepan Friedl, Jiri Sikora, Jan Korenek
2018 A conf
Configurable FPGA Packet Parser for Terabit Networks with Guaranteed Wire-Speed Throughput.
FPGA
Jakub Cabal, Pavel Benácek, Lukas Kekely, Michal Kekely, Viktor Pus, Jan Korenek
2018 C conf
General IDS Acceleration for High-Speed Networks.
ICCD
Jan Kucera, Lukas Kekely, Adam Piecek, Jan Korenek
2018 B conf
Live demonstration of FPGA based networking accelerator for 200 Gbps data transfers.
NOMS
Lukas Kekely, Martin Spinler, Stepan Friedl, Jiri Sikora, Jan Korenek
2018 C conf
Memory Aware Packet Matching Architecture for High-Speed Networks.
DSD
Michal Kekely, Lukas Kekely, Jan Korenek
2016 J jnl
Software Defined Monitoring of Application Protocols.
IEEE Trans. Computers
Lukas Kekely, Jan Kucera, Viktor Pus, Jan Korenek, Athanasios V. Vasilakos
2015 B conf
Hardware accelerated flow measurement of 100 Gb ethernet.
IM
Viktor Pus, Petr Velan, Lukas Kekely, Jan Korenek, Pavel Minarík
2014 C conf
CRC based hashing in FPGA using DSP blocks.
DDECS
Tomás Závodník, Lukas Kekely, Viktor Pus
2014 C conf
Design methodology of configurable high performance packet parser for FPGA.
DDECS
Viktor Pus, Lukas Kekely, Jan Korenek
2014 C conf
Fast lookup for dynamic packet filtering in FPGA.
DDECS
Lukas Kekely, Martin Zádník, Jirí Matousek, Jan Korenek
2014 A* conf
Software Defined Monitoring of application protocols.
INFOCOM
Lukas Kekely, Viktor Pus, Jan Korenek
2014 B conf
Trade-offs and progressive adoption of FPGA acceleration in network traffic monitoring.
FPL
Lukas Kekely, Viktor Pus, Pavel Benácek, Jan Korenek
2014 A conf
Using DSP blocks to compute CRC hash in FPGA (abstract only).
FPGA
Viktor Pus, Lukas Kekely, Tomás Závodník
2012 — conf
Low-latency modular packet header parser for FPGA.
ANCS
Viktor Pus, Lukas Kekely, Jan Korenek