Luis Parrilla - RankMe

35 papers B 4C 1Misc 1Journal 16Unranked 13

Year	Rank	Type	Title / Venue / Authors
2025	—	`conf`	1-D Convolutional Autoencoder for Fetal and Maternal ECG Classification Oriented to Hardware Implementation Acceleration. DCIS Rubén Padial-Allué, Alberto Martín-Martín, Encarnación Castillo, Uwe Meyer-Baese, Víctor Toral, Luis Parrilla, Antonio García
2025	J	`jnl`	Integration of Hardware Security Modules into BLE Beacons: Fundamentals and Use in a Secure and Private Geofencing Application. Internet Things Miguel Mesa-Simón, Antonio Escobar-Molero, Luis Parrilla, Diego P. Morales, José Antonio Álvarez-Bermejo, Francisco J. Romero
2025	J	`jnl`	Spiking Neural Networks for People Counting Based on FMCW Radar. IEEE Access Alberto Martín-Martín, Marta Verona-Almeida, Rubén Padial-Allué, Borja Saez, Javier Mendez, Encarnación Castillo, Luis Parrilla
2024	J	`jnl`	GenericSNN: A Framework for Easy Development of Spiking Neural Networks. IEEE Access Alberto Martín-Martín, Marta Verona-Almeida, Rubén Padial-Allué, Javier Mendez, Encarnación Castillo, Luis Parrilla
2024	J	`jnl`	Hardware Implementations of a Deep Learning Approach to Optimal Configuration of Reconfigurable Intelligence Surfaces. Sensors Alberto Martín-Martín, Rubén Padial-Allué, Encarnación Castillo, Luis Parrilla, Ignacio Parellada-Serrano, Alejandro Morán, Antonio García
2023	—	`conf`	Blockchain-based implementation of Tradable Green Certificates. PRIME Antonio Javier Cabrera Gutiérrez, Encarnación Castillo, Antonio Escobar-Molero, Diego Pedro Morales, Luis Parrilla
2023	J	`jnl`	Digital Implementation of Radial Basis Function Neural Networks Based on Stochastic Computing. IEEE J. Emerg. Sel. Topics Circuits Syst. Alejandro Morán, Luis Parrilla, Miquel Roca, Joan Font-Rosselló, Eugeni Isern, Vincent Canals
2023	J	`jnl`	Revisiting Multiple Ring Oscillator-Based True Random Generators to Achieve Compact Implementations on FPGAs for Cryptographic Applications. Cryptogr. Luis Parrilla, Antonio García, Encarnación Castillo, Juan Antonio López Ramos, Uwe Meyer-Baese
2023	J	`jnl`	Toward Sensor Measurement Reliability in Blockchains. Sensors Ernesto Gómez-Marín, Luis Parrilla, Jose L. Tejero López, Diego Pedro Morales, Encarnación Castillo
2022	J	`jnl`	Integration of Hardware Security Modules and Permissioned Blockchain in Industrial IoT Networks. IEEE Access Antonio Javier Cabrera Gutiérrez, Encarnación Castillo, Antonio Escobar-Molero, José Antonio Álvarez-Bermejo, Diego Pedro Morales, Luis Parrilla
2022	J	`jnl`	RESEKRA: Remote Enrollment Using SEaled Keys for Remote Attestation. Sensors Ernesto Gómez-Marín, Luis Parrilla, Gianfranco Mauro, Antonio Escobar-Molero, Diego Pedro Morales, Encarnación Castillo
2022	J	`jnl`	Table-Free Seed Generation for Hardware Newton-Raphson Square Root and Inverse Square Root Implementations in IoT Devices. IEEE Internet Things J. Luis Parrilla, Antonio Lloris, Encarnación Castillo, Antonio García
2021	—	`conf`	Window Polarization in PCA-based Analysis of Non-Invasive Fetal ECG recordings. DCIS Luis Oyarzún, Encarnación Castillo, Luis Parrilla, Antonio García
2020	—	`conf`	Privacy-enabled system based on Elliptic Curve Cryptography to reduce risks of contagion in pandemics. DCIS Luis Parrilla, Encarnación Castillo, Antonio García
2020	—	`conf`	Simple Single Particle Model for Interpreting Fast Charge Results in Intercalation Batteries. DCIS Juan Antonio López-Villanueva, Salvador Rodríguez-Bolívar, Luis Parrilla, César Fiñana
2017	J	`jnl`	A new area-efficient BCD-digit multiplier. Digit. Signal Process. Encarnación Castillo, Antonio Lloris-Ruíz, Diego Pedro Morales, Luis Parrilla, Antonio García, Guillermo Botella
2017	—	`conf`	Classification Algorithms for Fetal QRS Extraction in Abdominal ECG Signals. IWBBIO (1) Pedro Álvarez, Francisco J. Romero, Antonio García, Luis Parrilla, Encarnación Castillo, Diego Pedro Morales
2016	J	`jnl`	Comments on "Fast architecture for decimal digit multiplication". Microprocess. Microsystems Encarnación Castillo, Antonio Lloris-Ruíz, Antonio García, Luis Parrilla, Diego Pedro Morales
2015	J	`jnl`	Improvements for the applicability of power-watermarking to embedded IP cores protection: e-coreIPP. Digit. Signal Process. Luis Parrilla, Encarnación Castillo, Elias Todorovich, Antonio García, Diego Pedro Morales, Guillermo Botella
2013	J	`jnl`	Efficient wavelet-based ECG processing for single-lead FHR extraction. Digit. Signal Process. Encarnación Castillo, Diego Pedro Morales, Guillermo Botella Juan, Antonio García, Luis Parrilla, Alberto J. Palma
2013	J	`jnl`	Noise Suppression in ECG Signals through Efficient One-Step Wavelet Processing Techniques. J. Appl. Math. Encarnación Castillo, Diego Pedro Morales, Antonio García, Fernando Martínez-Martí, Luis Parrilla, Alberto J. Palma
2013	—	`conf`	One-step wavelet-based processing for wandering and noise removing in ECG signals. IWBBIO Encarnación Castillo, Diego Pedro Morales, Antonio García, Luis Parrilla, Nuria López-Ruiz, Alberto J. Palma
2007	J	`jnl`	IPP@HDL: Efficient Intellectual Property Protection Scheme for IP Cores. IEEE Trans. Very Large Scale Integr. Syst. Encarnación Castillo, Uwe Meyer-Bäse, Antonio García, Luis Parrilla, Antonio Lloris-Ruíz
2007	B	`conf`	Intellectual Property Protection of HDL IP Cores Through Automated Sognature Hosting. FPL Encarnación Castillo, Luis Parrilla, Antonio García, Uwe Meyer-Bäse, Antonio Lloris-Ruíz
2006	B	`conf`	IPP Watermarking Technique for IP Core Protection on FPL Devices. FPL Encarnación Castillo, Luis Parrilla, Antonio García, Antonio Lloris-Ruíz, Uwe Meyer-Bäse
2005	—	`conf`	Efficient Clock Distribution Scheme for VLSI RNS-Enabled Controllers. PATMOS Daniel González, Luis Parrilla, Antonio García, Encarnación Castillo, Antonio Lloris-Ruíz
2004	B	`conf`	Intellectual Property Protection for RNS Circuits on FPGAs. FPL Luis Parrilla, Encarnación Castillo, Antonio García, Antonio Lloris-Ruíz
2002	—	`conf`	A New Methodology for Efficient Synchronization of RNS-Based VLSI Systems. PATMOS Daniel González, Antonio García, Graham A. Jullien, Javier Ramírez, Luis Parrilla, Antonio Lloris-Ruíz
2001	—	`conf`	Implementation of the one dimensional discrete cosine transform using the residue number system. ICECS Pedro G. Fernández, Javier Ramírez, Antonio García, Luis Parrilla, Antonio Lloris-Ruíz
2000	C	`conf`	A new architecture to compute the discrete cosine transform using the quadratic residue number system. ISCAS Javier Ramírez Perez de Inestrosa, Antonio García, Pedro G. Fernández, Luis Parrilla, Antonio Lloris-Ruíz
2000	B	`conf`	Analysis of RNS-FPL Synergy for High Throughput DSP Applications: Discrete Wavelet Transform. FPL Javier Ramírez, Antonio García, Pedro G. Fernández, Luis Parrilla, Antonio Lloris-Ruíz
1999	—	`conf`	Adaptive Cooperation Between Processors in a Parallel Boltzmann Machine. IWANN (2) Julio Ortega, Luis Parrilla, José Luis Bernier, Consolación Gil, Begoña Pino, Mancia Anguita
1999	—	`conf`	Using PVM for Distributed Logic Minimization in a Network of Computers. PVM/MPI Luis Parrilla, Julio Ortega, Antonio Lloris-Ruíz
1998	—	`conf`	Testability of AND-EXOR logic vs. AND-OR logic. ICECS Luis Parrilla, Julio Ortega, Antonio Lloris-Ruíz
1997	Misc	`conf`	Modified Boltzmann Machine for an Efficient Distributed Implementation. IWANN Julio Ortega, Luis Parrilla, Alberto Prieto, Antonio Lloris-Ruíz, Carlos García Puntonet