Luis J. Saiz-Adalid

24 papers A 1B 3C 1Misc 4Journal 8Unranked 7
YearRankTypeTitle / Venue / Authors
2025 B conf
Can C-Based ECC Models Leverage High-Level Synthesis? Evaluating Description Variants for Efficient Circuit Implementations.
SAFECOMP
Joaquin Gracia-Moran, Juan-Carlos Ruiz-Garcia, David de Andrés, Luis J. Saiz-Adalid
2025 — conf
Initial Insights into Synthesis Overheads Caused by C-Based Error Correction Codes Implementations.
EDCC-C
Joaquin Gracia-Moran, David de Andrés, Luis J. Saiz-Adalid, Juan Carlos Ruiz, Juan-Carlos Baraza-Calvo, Daniel Gil-Tomas, Pedro J. Gil-Vicente
2025 — conf
Towards SW-Based Robustness Assessment of HW Accelerators for Quantized CNNs.
EDCC-C
Juan Carlos Ruiz, David de Andrés, Luis J. Saiz-Adalid, Joaquin Gracia-Moran
2025 — conf
Towards a Novel 8-Bit Floating-Point Format to Increase Robustness in Convolutional Neural Networks.
EDCC-C
Luis J. Saiz-Adalid, Juan-Carlos Ruiz-Garcia, Joaquin Gracia-Moran, David de Andrés, Juan-Carlos Baraza-Calvo, Daniel Gil-Tomas, Pedro J. Gil-Vicente
2024 J jnl
A Hybrid Technique Based on ECC and Hardened Cells for Tolerating Random Multiple-Bit Upsets in SRAM Arrays.
IEEE Access
Daniel Gil-Tomas, Luis J. Saiz-Adalid, Joaquin Gracia-Moran, Juan-Carlos Baraza-Calvo, Pedro J. Gil-Vicente
2024 — conf
Allocating ECC parity bits into BF16-encoded CNN parameters: A practical experience report.
LADC
Joaquin Gracia-Moran, Juan Carlos Ruiz, David de Andrés, Luis J. Saiz-Adalid
2024 B conf
In-Memory Zero-Space Floating-Point-Based CNN Protection Using Non-significant and Invariant Bits.
SAFECOMP
Juan Carlos Ruiz, David de Andrés, Luis J. Saiz-Adalid, Joaquin Gracia-Moran
2024 Misc conf
Zero-Space In-Weight and In-Bias Protection for Floating-Point-based CNNs.
EDCC
Juan Carlos Ruiz, David de Andrés, Luis J. Saiz-Adalid, Joaquin Gracia-Moran
2019 J jnl
Ultrafast Codes for Multiple Adjacent Error Correction and Double Error Detection.
IEEE Access
Luis J. Saiz-Adalid, Joaquin Gracia-Moran, Daniel Gil-Tomas, Juan-Carlos Baraza-Calvo, Pedro J. Gil-Vicente
2018 — conf
Correction of Adjacent Errors with Low Redundant Matrix Error Correction Codes.
LADC
Joaquin Gracia-Moran, Luis J. Saiz-Adalid, Juan-Carlos Baraza-Calvo, Pedro J. Gil
2018 J jnl
Improving Error Correction Codes for Multiple-Cell Upsets in Space Applications.
IEEE Trans. Very Large Scale Integr. Syst.
Joaquin Gracia-Moran, Luis J. Saiz-Adalid, Daniel Gil-Tomas, Pedro J. Gil-Vicente
2016 J jnl
Injecting Intermittent Faults for the Dependability Assessment of a Fault-Tolerant Microcomputer System.
IEEE Trans. Reliab.
Daniel Gil-Tomas, Joaquin Gracia-Moran, Juan-Carlos Baraza-Calvo, Luis J. Saiz-Adalid, Pedro J. Gil-Vicente
2016 Misc conf
Ultrafast Error Correction Codes for Double Error Detection/Correction.
EDCC
Luis J. Saiz-Adalid, Pedro J. Gil, Juan Carlos Ruiz, Joaquin Gracia-Moran, Daniel Gil-Tomas, Juan-Carlos Baraza-Calvo
2015 J jnl
MCU Tolerance in SRAMs Through Low-Redundancy Triple Adjacent Error Correction.
IEEE Trans. Very Large Scale Integr. Syst.
Luis J. Saiz-Adalid, Pedro Reviriego, Pedro J. Gil, Salvatore Pontarelli, Juan Antonio Maestro
2015 Misc conf
Ultrafast Single Error Correction Codes for Protecting Processor Registers.
EDCC
Luis J. Saiz-Adalid, Pedro J. Gil, Joaquin Gracia-Moran, Daniel Gil-Tomas, Juan-Carlos Baraza-Calvo
2014 J jnl
Effects of Intermittent Faults on the Reliability of a Reduced Instruction Set Computing (RISC) Microprocessor.
IEEE Trans. Reliab.
Joaquin Gracia-Moran, Juan-Carlos Baraza-Calvo, Daniel Gil-Tomas, Luis J. Saiz-Adalid, Pedro J. Gil-Vicente
2014 Misc conf
Modified Hamming Codes to Enhance Short Burst Error Detection in Semiconductor Memories (Short Paper).
EDCC
Luis J. Saiz-Adalid, Pedro J. Gil, Juan-Carlos Baraza-Calvo, Juan-Carlos Ruiz-Garcia, Daniel Gil-Tomas, Joaquin Gracia-Moran
2013 — conf
Defining a Representative and Low Cost Fault Model Set for Intermittent Faults in Microprocessor Buses.
LADC
Joaquin Gracia-Moran, Daniel Gil-Tomas, Luis J. Saiz-Adalid, Juan-Carlos Baraza-Calvo, Pedro J. Gil-Vicente
2013 B conf
Flexible Unequal Error Control Codes with Selectable Error Detection and Correction Levels.
SAFECOMP
Luis J. Saiz-Adalid, Pedro J. Gil-Vicente, Juan-Carlos Ruiz-Garcia, Daniel Gil-Tomas, Juan Carlos Baraza, Joaquin Gracia-Moran
2013 — conf
Using Interleaving to Avoid the Effects of Multiple Adjacent Faults in On-Chip Interconnection Lines.
EWDC
Luis J. Saiz-Adalid, Pedro J. Gil, Joaquin Gracia-Moran, Juan-Carlos Baraza-Calvo
2012 J jnl
Analyzing the Impact of Intermittent Faults on Microprocessors Applying Fault Injection.
IEEE Des. Test
Daniel Gil-Tomas, Joaquin Gracia-Moran, Juan-Carlos Baraza-Calvo, Luis J. Saiz-Adalid, Pedro J. Gil-Vicente
2012 J jnl
Studying the effects of intermittent faults on a microcontroller.
Microelectron. Reliab.
Daniel Gil-Tomas, Joaquin Gracia-Moran, Juan-Carlos Baraza-Calvo, Luis J. Saiz-Adalid, Pedro J. Gil-Vicente
2010 A conf
Experimental validation of a fault tolerant microcomputer system against intermittent faults.
DSN
Joaquin Gracia-Moran, Daniel Gil-Tomas, Luis J. Saiz-Adalid, Juan Carlos Baraza, Pedro J. Gil-Vicente
2010 C conf
Searching Representative and Low Cost Fault Models for Intermittent Faults in Microcontrollers: A Case Study.
PRDC
Joaquin Gracia-Moran, Daniel Gil-Tomas, Juan Carlos Baraza, Luis J. Saiz-Adalid, Pedro J. Gil-Vicente