Luis Entrena

76 papers A 5B 6C 22Misc 1Journal 23Unranked 19
YearRankTypeTitle / Venue / Authors
2025 — conf
Reliability Assessment of AMD MicroBlaze-V TMR Architecture Using Fault Injection.
DFT
Jorge Cano-Páez, Luis Entrena, Almudena Lindoso
2024 J jnl
Analysing the radiation reliability, performance and energy consumption of low-power SoC through heterogeneous parallelism.
Sustain. Comput. Informatics Syst.
José M. Badía, German Leon, Mario García-Valderas, Jose A. Belloch, Almudena Lindoso, Luis Entrena
2024 J jnl
Comparative analysis of soft-error sensitivity in LU decomposition algorithms on diverse GPUs.
J. Supercomput.
German Leon, José M. Badía, Jose A. Belloch, Almudena Lindoso, Luis Entrena
2024 J jnl
Error Mitigation Using Optimized Redundancy for Composite Algorithms in FPGAs.
IEEE Trans. Aerosp. Electron. Syst.
Luis Ángel García-Astudillo, Almudena Lindoso, Luis Entrena
2023 J jnl
Formal Verification of Fault-Tolerant Hardware Designs.
IEEE Access
Luis Entrena, Antonio J. Sanchez-Clemente, Luis Ángel García-Astudillo, Marta Portela-García, Mario García-Valderas, Almudena Lindoso, Roberto Sarmiento
2023 J jnl
Supervised Triple Macrosynchronized Lockstep (STMLS) Architecture for Multicore Processors.
IEEE Access
Pablo M. Aviles, Jose A. Belloch, Luis Entrena, Almudena Lindoso
2023 J jnl
Using Approximate Circuits Against Hardware Trojans.
IEEE Des. Test
Honorio Martín, Sophie Dupuis, Giorgio Di Natale, Luis Entrena
2022 B conf
Impact of Atmospheric and Space Radiation on Sensitive Electronic Devices.
ETS
Lucas Matana Luza, Frederic Wrobel, Luis Entrena, Luigi Dilillo
2022 J jnl
Reduced Resolution Redundancy: A Novel Approximate Error Mitigation Technique.
IEEE Access
Luis Ángel García-Astudillo, Luis Entrena, Almudena Lindoso, Honorio Martín
2020 J jnl
A True Random Number Generator Based on Gait Data for the Internet of You.
IEEE Access
Carmen Camara, Honorio Martín, Pedro Peris-Lopez, Luis Entrena
2020 — conf
Evaluation of a Reduced Precision Redundancy FFT Design.
DCIS
Luis Ángel García-Astudillo, Almudena Lindoso, Marta Portela, Luis Entrena
2018 C conf
A Novel Use of Approximate Circuits to Thwart Hardware Trojan Insertion and Provide Obfuscation.
IOLTS
Honorio Martín, Luis Entrena, Sophie Dupuis, Giorgio Di Natale
2018 — conf
Approximate TMR for selective error mitigation in FPGAs based on testability analysis.
AHS
Antonio Sanchez-Clemente, Luis Entrena, Fernanda Lima Kastensmidt
2018 J jnl
On the Entropy of Oscillator-Based True Random Number Generators under Ionizing Radiation.
Entropy
Honorio Martín, Pedro Martín-Holgado, Pedro Peris-Lopez, Yolanda Morilla, Luis Entrena
2018 J jnl
PTM-based hybrid error-detection architecture for ARM microprocessors.
Microelectron. Reliab.
Manuel Peña-Fernandez, Almudena Lindoso, Luis Entrena, Mario García-Valderas, S. Philippe, Yolanda Morilla, Pedro Martín-Holgado
2018 J jnl
Towards a Dependable True Random Number Generator With Self-Repair Capabilities.
IEEE Trans. Circuits Syst. I Regul. Pap.
Honorio Martín, Giorgio Di Natale, Luis Entrena
2016 J jnl
A Hardware-Software Approach for On-Line Soft Error Mitigation in Interrupt-Driven Applications.
IEEE Trans. Dependable Secur. Comput.
Antonio Martínez-Álvarez, Felipe Restrepo-Calle, Sergio Cuenca-Asensi, Leonardo M. Reyneri, Almudena Lindoso, Luis Entrena
2016 J jnl
Error Mitigation Using Approximate Logic Circuits: A Comparison of Probabilistic and Evolutionary Approaches.
IEEE Trans. Reliab.
Antonio Sanchez-Clemente, Luis Entrena, Radek Hrbacek, Lukás Sekanina
2016 J jnl
Online Test of Control Flow Errors: A New Debug Interface-Based Approach.
IEEE Trans. Computers
Boyang Du, Matteo Sonza Reorda, Luca Sterpone, Luis Parra, Marta Portela-García, Almudena Lindoso, Luis Entrena
2014 J jnl
A method to assess the robustness of cryptographic circuits at the design stage.
Microelectron. J.
M. Arévalo-Garbayo, Marta Portela-García, Mario García-Valderas, Celia López-Ongil, Luis Entrena
2014 C conf
A new solution to on-line detection of Control Flow Errors.
IOLTS
Boyang Du, Matteo Sonza Reorda, Luca Sterpone, Luis Parra, Marta Portela-García, Almudena Lindoso, Luis Entrena
2014 C conf
Error masking with approximate logic circuits using dynamic probability estimations.
IOLTS
Antonio Sanchez-Clemente, Luis Entrena, Mario García-Valderas
2013 C conf
Exploiting the debug interface to support on-line test of control flow errors.
IOLTS
Boyang Du, Matteo Sonza Reorda, Luca Sterpone, Luis Parra, Marta Portela-García, Almudena Lindoso, Luis Entrena
2013 — conf
Fast fault injection techniques using FPGAs.
LATW
Luis Entrena
2012 J jnl
Evaluating the Effectiveness of a Software-Based Technique Under SEEs Using FPGA-Based Fault Injection Approach.
J. Electron. Test.
Marta Portela-García, Almudena Lindoso, Luis Entrena, Mario García-Valderas, Celia López-Ongil, N. Marroni, Bernardo Pianta, Letícia Maria Bolzani Poehls, Fabian Vargas
2012 C conf
Logic masking for SET Mitigation Using Approximate Logic Circuits.
IOLTS
Antonio Sanchez-Clemente, Luis Entrena, Mario García-Valderas, Celia López-Ongil
2012 J jnl
On the use of embedded debug features for permanent and transient fault resilience in microprocessors.
Microprocess. Microsystems
Marta Portela-García, Michelangelo Grosso, M. Gallardo-Campos, Matteo Sonza Reorda, Luis Entrena, Mario García-Valderas, Celia López-Ongil
2012 C conf
SEU sensitivity of robust communication protocols.
IOLTS
Celia López-Ongil, Marta Portela-García, Mario García-Valderas, Anna Vaskova, Luis Entrena, Joaquín Rivas-Abalo, Alberto Martín-Ortega, Javier Martinez-Oter, S. Rodriguez-Bustabad, Ignacio Arruego
2012 J jnl
Soft Error Sensitivity Evaluation of Microprocessors by Multilevel Emulation-Based Fault Injection.
IEEE Trans. Computers
Luis Entrena, Mario García-Valderas, Raúl Fernández Cardenal, Almudena Lindoso, Marta Portela-García, Celia López-Ongil
2011 C conf
AKARI-X: A pseudorandom number generator for secure lightweight systems.
IOLTS
Honorio Martín, Enrique San Millán, Luis Entrena, Julio César Hernández Castro, Pedro Peris-Lopez
2011 C conf
Accelerating secure circuit design with hardware implementation of Diehard Battery of tests of randomness.
IOLTS
Anna Vaskova, Celia López-Ongil, Enrique San Millán, Alejandro Jiménez-Horas, Luis Entrena
2011 C conf
Evaluation techniques for on-line testing of robust systems based on critical tasks distribution.
IOLTS
Anna Vaskova, Celia López-Ongil, Mario García-Valderas, Marta Portela-García, Luis Entrena
2011 J jnl
Fault Injection in Modern Microprocessors Using On-Chip Debugging Infrastructures.
IEEE Trans. Dependable Secur. Comput.
Marta Portela-García, Celia López-Ongil, Mario García-Valderas, Luis Entrena
2011 — conf
Using an FPGA-based fault injection technique to evaluate software robustness under SEEs: A case study.
LATW
Marta Portela-García, Almudena Lindoso, Luis Entrena, Mario García-Valderas, Celia López-Ongil, Bernardo Pianta, Letícia Maria Bolzani Poehls, Fabian Vargas
2010 C conf
An on-line fault detection technique based on embedded debug features.
IOLTS
Michelangelo Grosso, Matteo Sonza Reorda, Marta Portela-García, Mario García-Valderas, Celia López-Ongil, Luis Entrena
2010 — conf
Cryptographically secure pseudo-random bit generator for RFID tags.
ICITST
Pedro Peris-Lopez, Enrique San Millán, Jan C. A. van der Lubbe, Luis Entrena
2010 C conf
Robust cryptographic ciphers with on-line statistical properties validation.
IOLTS
Anna Vaskova, Celia López-Ongil, Alejandro Jiménez-Horas, Enrique San Millán, Luis Entrena
2009 C conf
Briefing power/reliability optimization in embedded software design.
IOLTS
Fabian Vargas, Claudia A. Rocha, Bernardo Pianta, Marta Portela-García, Celia López-Ongil, Mario García-Valderas, Luis Entrena
2009 C conf
In-depth analysis of digital circuits against soft errors for selective hardening.
IOLTS
Mario García-Valderas, Marta Portela-García, Celia López-Ongil, Luis Entrena
2009 C conf
Pseudo-random number generation applied to robust modern cryptography: A new technique for block ciphers.
IOLTS
Alejandro Jiménez-Horas, Enrique San Millán, Celia López-Ongil, Marta Portela-García, Mario García-Valderas, Luis Entrena
2009 J jnl
SET Emulation Under a Quantized Delay Model.
J. Electron. Test.
Mario García-Valderas, Luis Entrena, Raúl Fernández Cardenal, Celia López-Ongil, Marta Portela-García
2009 — conf
Study of SEU effects in a Turbo Decoder Bit Error Rate.
LATW
Marta Portela-García, Mario García-Valderas, Celia López-Ongil, Luis Entrena, B. Lestriez, Luis Berrojo
2008 B conf
Coarse-grain dynamically reconfigurable coprocessor for image processing in SOPC.
FPL
Almudena Lindoso, Luis Entrena, Juan Izquierdo, Judith Liu-Jimenez
2008 C conf
Logic Transformations by Multiple Wire Network Addition.
DSD
Enrique San Millán, Luis Entrena, José Alberto Espejo
2008 C conf
Smart Hardening for Round-based Encryption Algorithms: Application to Advanced Encryption Standard.
IOLTS
Celia López-Ongil, Alejandro Jiménez-Horas, Marta Portela-García, Mario García-Valderas, Enrique San Millán, Luis Entrena
2007 C conf
A Rapid Fault Injection Approach for Measuring SEU Sensitivity in Complex Processors.
IOLTS
Marta Portela-García, Celia López-Ongil, Mario García-Valderas, Luis Entrena
2007 — conf
Correlation-Based Fingerprint Matching with Orientation Field Alignment.
ICB
Almudena Lindoso, Luis Entrena, Judith Liu-Jimenez, Enrique San Millán
2007 J jnl
High performance FPGA-based image correlation.
J. Real Time Image Process.
Almudena Lindoso, Luis Entrena
2007 J jnl
Low power data processing system with self-reconfigurable architecture.
J. Syst. Archit.
Michael G. Lorenz, Luis Mengibar, Enrique San Millán, Luis Entrena
2007 — conf
SET Emulation Under a Quantized Delay Model.
DFT
Mario García-Valderas, Raúl Fernández Cardenal, Celia López-Ongil, Marta Portela-García, Luis Entrena
2007 C conf
Wavelet-Based Fingerprint Region Selection.
CAIP
Almudena Lindoso, Luis Entrena, Judith Liu-Jimenez
2006 C conf
Emulation-based Fault Injection in Circuits with Embedded Memories.
IOLTS
Mario García-Valderas, Marta Portela-García, Celia López-Ongil, Luis Entrena
2006 B conf
Fault Injection-based Reliability Evaluation of SoPCs.
ETS
Matteo Sonza Reorda, Luca Sterpone, Massimo Violante, Marta Portela-García, Celia López-Ongil, Luis Entrena
2005 — conf
Correlation-Based Fingerprint Matching Using FPGAs.
FPT
Almudena Lindoso, Luis Entrena, Celia López-Ongil, Judith Liu-Jimenez
2004 — conf
Architectures for Biometric Match-on-Token Solutions.
ECCV Workshop BioAW
Raul Sánchez-Reillo, Judith Liu-Jimenez, Luis Entrena
2004 B conf
FPGA Implementation of Biometric Authentication System Based on Hand Geometry.
FPL
Celia López-Ongil, Raul Sánchez-Reillo, Judith Liu-Jimenez, Fernando Casado, Leslie Sánchez, Luis Entrena
2004 B conf
Power Consumption Reduction Through Dynamic Reconfiguration.
FPL
Michael G. Lorenz, Luis Mengibar, Mario García-Valderas, Luis Entrena
2004 C conf
Transient Fault Emulation of Hardened Circuits in FPGA Platforms.
IOLTS
Mario García-Valderas, Celia López-Ongil, Marta Portela-García, Luis Entrena
2003 B conf
Data Processing System With Self-reconfigurable Architecture, for Low Cost, Low Power Applications.
FPL
Michael G. Lorenz, Luis Mengibar, Luis Entrena, Raul Sánchez-Reillo
2003 — conf
State Encoding for Low-Power FSMs in FPGA.
PATMOS
Luis Mengibar, Luis Entrena, Michael G. Lorenz, Raul Sánchez-Reillo
2003 J jnl
Theoretical comparison between sequential redundancy addition and removal and retiming optimization techniques.
J. Syst. Archit.
Enrique San Millán, Luis Entrena, José Alberto Espejo, Celia López
2002 Misc conf
An Industrial Environment for High-Level Fault-Tolerant Structures Insertion and Validation.
VTS
Luis Berrojo, Isabel González, Fulvio Corno, Matteo Sonza Reorda, Giovanni Squillero, Luis Entrena, Celia López
2002 — conf
Analysis of the Equivalences and Dominances of Transient Faults at the RT Level.
IOLTW
Luis Berrojo, Isabel González, Luis Entrena, Celia López, Fulvio Corno, Matteo Sonza Reorda, Giovanni Squillero
2002 A conf
New Techniques for Speeding-Up Fault-Injection Campaigns.
DATE
Luis Berrojo, Isabel González, Fulvio Corno, Matteo Sonza Reorda, Giovanni Squillero, Luis Entrena, Celia López
2001 — conf
Automatic Insertion of Fault-Tolerant Structures at the RT Level.
IOLTW
Luis Entrena, Celia López, Emilio Olías
2001 — conf
Functional extension of structural logic optimization techniques.
ASP-DAC
José Alberto Espejo, Luis Entrena, Enrique San Millán, Emilio Olías
2001 A conf
Generalized reasoning scheme for redundancy addition and removal logic optimization.
DATE
José Alberto Espejo, Luis Entrena, Enrique San Millán, Emilio Olías
2001 — conf
Logic Optimization of Unidirectional Circuits with Structural Methods.
IOLTW
Luis Entrena, Celia López, Emilio Olías, Enrique San Millán, José Alberto Espejo
2001 A conf
On the Optimization Power of Redundancy Addition and Removal Techniques for Sequential Circuits.
ICCAD
Enrique San Millán, Luis Entrena, José Alberto Espejo
2001 C conf
On the Optimization Power of Redundancy Addition and Removal for Sequential Logic Optimization.
DSD
Enrique San Millán, Luis Entrena, José Alberto Espejo
1999 A conf
Integrating Symbolic Techniques in ATPG-Based Sequential Logic Optimization.
DATE
Enrique San Millán, Luis Entrena, José Alberto Espejo, Silvia Chiusano, Fulvio Corno
1999 — conf
Logic Restructuring for MUX-Based FPGAs.
EUROMICRO
José Alberto Espejo, Luis Entrena, Enrique San Millán, Emilio Olías
1996 — conf
Timing optimization by an improved redundancy addition and removal technique.
EURO-DAC
Luis Entrena, Emilio Olías, Javier Uceda, José Alberto Espejo
1995 — conf
An effective system development environment based on VHDL prototyping.
EURO-DAC
Serafín Olcoz, Luis Entrena, Luis Berrojo
1995 C conf
VHDL virtual prototyping.
RSP
Serafín Olcoz, Luis Entrena, Luis Berrojo
1993 A conf
Sequential logic optimization by redundancy addition and removal.
ICCAD
Luis Entrena, Kwang-Ting Cheng