Luis Alberto Aranda

12 papers Journal 12
YearRankTypeTitle / Venue / Authors
2026 J jnl
LLNN: A Scalable LUT-Based Logic Neural Network Architecture for FPGAs.
IEEE Trans. Circuits Syst. I Regul. Pap.
Iván Ramírez, Francisco José García-Espinosa, David Concha, Luis Alberto Aranda, Emanuele Schiavi
2025 J jnl
Logic Neural Networks for Efficient FPGA Implementation.
IEEE Trans. Circuits Syst. I Regul. Pap.
Iván Ramírez, Francisco José García-Espinosa, David Concha, Luis Alberto Aranda
2022 J jnl
ACME-2: Improving the Extraction of Essential Bits in Xilinx SRAM-Based FPGAs.
IEEE Trans. Circuits Syst. II Express Briefs
Luis Alberto Aranda, Oscar Ruano, Francisco Garcia-Herrero, Juan Antonio Maestro
2021 J jnl
Fault Injection Emulation for Systems in FPGAs: Tools, Techniques and Methodology, a Tutorial.
Sensors
Oscar Ruano, Francisco Garcia-Herrero, Luis Alberto Aranda, Alfonso Sánchez-Macián, Laura Rodriguez, Juan Antonio Maestro
2021 J jnl
Reliability Analysis of ASIC Designs With Xilinx SRAM-Based FPGAs.
IEEE Access
Luis Alberto Aranda, Oscar Ruano, Francisco Garcia-Herrero, Juan Antonio Maestro
2020 J jnl
An Algorithmic-Based Fault Detection Technique for the 1-D Discrete Cosine Transform.
IEEE Trans. Very Large Scale Integr. Syst.
Luis Alberto Aranda, Alfonso Sánchez-Macián, Juan Antonio Maestro
2020 J jnl
Radiation Hardened Digital Direct Synthesizer With CORDIC for Spaceborne Applications.
IEEE Access
Luis Alberto Aranda, Francisco Garcia-Herrero, Luis Esteban, Alfonso Sánchez-Macián, Juan Antonio Maestro
2020 J jnl
Toward a Fault-Tolerant Star Tracker for Small Satellite Applications.
IEEE Trans. Aerosp. Electron. Syst.
Luis Alberto Aranda, Pedro Reviriego, Juan Antonio Maestro
2019 J jnl
ACME: A Tool to Improve Configuration Memory Fault Injection in SRAM-Based FPGAs.
IEEE Access
Luis Alberto Aranda, Alfonso Sánchez-Macián, Juan Antonio Maestro
2019 J jnl
Enhancing Instruction TLB Resilience to Soft Errors.
IEEE Trans. Computers
Alfonso Sánchez-Macián, Luis Alberto Aranda, Pedro Reviriego, Vahdaneh Kiani, Juan Antonio Maestro
2019 J jnl
Protection Scheme for Star Tracker Images.
IEEE Trans. Aerosp. Electron. Syst.
Luis Alberto Aranda, Pedro Reviriego, Ricardo Gonzalez-Toral, Juan Antonio Maestro
2018 J jnl
A Comparison of Dual Modular Redundancy and Concurrent Error Detection in Finite Impulse Response Filters Implemented in SRAM-Based FPGAs Through Fault Injection.
IEEE Trans. Circuits Syst. II Express Briefs
Luis Alberto Aranda, Pedro Reviriego, Juan Antonio Maestro