Luis A. Plana

77 papers A* 1A 3B 6C 14Misc 2Journal 27Unranked 24
YearRankTypeTitle / Venue / Authors
2023 — conf
A High-Throughput Low-Latency Interface Board for SpiNNaker-in-the-loop Real-Time Systems.
ICONS
Juan Pablo Romero Bermudez, Luis A. Plana, Andrew Rowley, Mikael Hessel, Jens Egholm Pedersen, Steve B. Furber, Jörg Conradt
2023 — conf
Optimizations for Very Long and Sparse Vector Operations on a RISC-V VPU: A Work-in-Progress.
ISC Workshops
Gopinath Mahale, Tejas Limbasiya, Muhammad Asad Aleem, Luis A. Plana, Aleksandar Duricic, Alireza Monemi, Xabier Abancens, Teresa Cervero, John D. Davis
2020 J jnl
Analysis of software and hardware-accelerated approaches to the simulation of unconventional interconnection networks.
Simul. Model. Pract. Theory
Mohsen Ghasempour, Jonathan Heathcote, Javier Navaridas, Luis A. Plana, Jim D. Garside, Mikel Luján
2020 J jnl
spiNNlink: FPGA-Based Interconnect for the Million-Core SpiNNaker System.
IEEE Access
Luis A. Plana, Jim D. Garside, Jonathan Heathcote, Jeffrey Pepper, Steve Temple, Simon Davidson, Mikel Luján, Steve B. Furber
2019 J jnl
Dynamic Power Management for Neuromorphic Many-Core Systems.
CoRR
Sebastian Höppner, Bernhard Vogginger, Yexin Yan, Andreas Dixius, Stefan Scholze, Johannes Partzsch, Felix Neumaerker, Stephan Hartmann, Stefan Schiefer, Georg Ellguth, Love Cederstroem, Luis A. Plana, Jim D. Garside, Steve B. Furber, Christian Mayr
2019 J jnl
Dynamic Power Management for Neuromorphic Many-Core Systems.
IEEE Trans. Circuits Syst. I Regul. Pap.
Sebastian Höppner, Bernhard Vogginger, Yexin Yan, Andreas Dixius, Stefan Scholze, Johannes Partzsch, Felix Neumärker, Stephan Hartmann, Stefan Schiefer, Georg Ellguth, Love Cederstroem, Luis A. Plana, Jim D. Garside, Steve B. Furber, Christian Mayr
2019 J jnl
Real-Time Cortical Simulation on Neuromorphic Hardware.
CoRR
Oliver Rhodes, Luca Peres, Andrew G. D. Rowley, Andrew Gait, Luis A. Plana, Christian Y. A. Brenninkmeijer, Steve B. Furber
2018 — conf
Network-on-chip evaluation for a novel neural architecture.
CF
Markos Kynigos, Javier Navaridas, Luis A. Plana, Steve B. Furber
2018 J jnl
Parallel Distribution of an Inner Hair Cell and Auditory Nerve Model for Real-Time Application.
IEEE Trans. Biomed. Circuits Syst.
Robert James, Jim D. Garside, Luis A. Plana, Andrew Rowley, Steve B. Furber
2018 C conf
Performance Comparison of Time-Step-Driven versus Event-Driven Neural State Update Approaches in SpiNNaker.
ISCAS
Amirreza Yousefzadeh, Mikel Soto, Teresa Serrano-Gotarredona, Francesco Galluppi, Luis A. Plana, Steve B. Furber, Bernabé Linares-Barranco
2018 J jnl
SpiNNTools: The Execution Engine for the SpiNNaker Platform.
CoRR
Andrew G. D. Rowley, Christian Y. A. Brenninkmeijer, Simon Davidson, Donal Fellows, Andrew Gait, David R. Lester, Luis A. Plana, Oliver Rhodes, Alan B. Stokes, Steve B. Furber
2017 B conf
Asynchronous interface FIFO design on FPGA for high-throughput NRZ synchronisation.
FPL
Gengting Liu, Jim D. Garside, Steve B. Furber, Luis A. Plana, Dirk Koch
2017 C conf
Dynamic voltage and frequency scaling for neuromorphic many-core systems.
ISCAS
Sebastian Höppner, Yexin Yan, Bernhard Vogginger, Andreas Dixius, Johannes Partzsch, Felix Neumärker, Stephan Hartmann, Stefan Schiefer, Stefan Scholze, Georg Ellguth, Love Cederstroem, Matthias Eberlein, Christian Mayr, Steve Temple, Luis A. Plana, Jim D. Garside, Simon Davidson, David R. Lester, Steve B. Furber
2017 C conf
Live demonstration: Dynamic voltage and frequency scaling for neuromorphic many-core systems.
ISCAS
Sebastian Höppner, Yexin Yan, Bernhard Vogginger, Andreas Dixius, Johannes Partzsch, Prateek Joshi, Felix Neumärker, Stephan Hartmann, Stefan Schiefer, Stefan Scholze, Georg Ellguth, Love Cederstroem, Matthias Eberlein, Christian Mayr, Steve Temple, Luis A. Plana, Jim D. Garside, Simon Davidson, David R. Lester, Steve B. Furber
2017 C conf
Live demonstration: Multiplexing AER asynchronous channels over LVDS links with flow-control and clock-correction for scalable neuromorphic systems.
ISCAS
Amirreza Yousefzadeh, Miroslaw Jablonski, Taras Iakymchuk, Alejandro Linares-Barranco, Alfredo Rosado Muñoz, Luis A. Plana, Teresa Serrano-Gotarredona, Steve B. Furber, Bernabé Linares-Barranco
2017 C conf
Multiplexing AER asynchronous channels over LVDS links with flow-control and clock-correction for scalable neuromorphic systems.
ISCAS
Amirreza Yousefzadeh, Miroslaw Jablonski, Taras Iakymchuk, Alejandro Linares-Barranco, Alfredo Rosado Muñoz, Luis A. Plana, Teresa Serrano-Gotarredona, Stephen B. Furber, Bernabé Linares-Barranco
2017 J jnl
On Multiple AER Handshaking Channels Over High-Speed Bit-Serial Bidirectional LVDS Links With Flow-Control and Clock-Correction on Commercial FPGAs for Scalable Neuromorphic Systems.
IEEE Trans. Biomed. Circuits Syst.
Amirreza Yousefzadeh, Miroslaw Jablonski, Taras Iakymchuk, Alejandro Linares-Barranco, Alfredo Rosado, Luis A. Plana, Steve Temple, Teresa Serrano-Gotarredona, Steve B. Furber, Bernabé Linares-Barranco
2017 — conf
Parallel distribution of an inner hair cell and auditory nerve model for real-time application.
BioCAS
Robert James, Jim D. Garside, Michael Hopkins, Luis A. Plana, Steve Temple, Simon Davidson, Steve B. Furber
2016 J jnl
Fast Predictive Handshaking in Synchronous FPGAs for Fully Asynchronous Multisymbol Chip Links: Application to SpiNNaker 2-of-7 Links.
IEEE Trans. Circuits Syst. II Express Briefs
Amirreza Yousefzadeh, Luis A. Plana, Steve Temple, Teresa Serrano-Gotarredona, Steve B. Furber, Bernabé Linares-Barranco
2016 C conf
High performance computing on SpiNNaker neuromorphic platform: A case study for energy efficient image processing.
IPCCC
Indar Sugiarto, Gengting Liu, Simon Davidson, Luis A. Plana, Steve B. Furber
2015 Misc conf
Accelerating Interconnect Analysis Using High-Level HDLs and FPGA, SpiNNaker as a Case Study.
FCCM
Mohsen Ghasempour, Jonathan Heathcote, Javier Navaridas, Luis A. Plana, Jim D. Garside, Mikel Luján
2015 — conf
Analysis of FPGA and software approaches to simulate unconventional computer architectures.
ReConFig
Mohsen Ghasempour, Jonathan Heathcote, Javier Navaridas, Luis A. Plana, Jim D. Garside, Mikel Luján
2015 C conf
ConvNets experiments on SpiNNaker.
ISCAS
Teresa Serrano-Gotarredona, Bernabé Linares-Barranco, Francesco Galluppi, Luis A. Plana, Stephen B. Furber
2015 J jnl
SpiNNaker - Programming Model.
IEEE Trans. Computers
Andrew D. Brown, Stephen B. Furber, Jeffrey S. Reeve, Jim D. Garside, Kier J. Dugan, Luis A. Plana, Steve Temple
2015 J jnl
SpiNNaker: Enhanced multicast routing.
Parallel Comput.
Javier Navaridas, Mikel Luján, Luis A. Plana, Steve Temple, Steve B. Furber
2014 A* conf
Event-based neural computing on an autonomous mobile platform.
ICRA
Francesco Galluppi, Christian Denk, Matthias C. Meiner, Terrence C. Stewart, Luis A. Plana, Chris Eliasmith, Stephen B. Furber, Jörg Conradt
2014 — conf
On generating multicast routes for SpiNNaker.
Conf. Computing Frontiers
Javier Navaridas, Mikel Luján, Luis A. Plana, Steve Temple, Steve B. Furber
2014 J jnl
The SpiNNaker Project.
Proc. IEEE
Steve B. Furber, Francesco Galluppi, Steve Temple, Luis A. Plana
2013 B conf
A location-independent direct link neuromorphic interface.
IJCNN
Alexander D. Rast, Johannes Partzsch, Christian Mayr, Johannes Schemmel, Stefan Hartmann, Luis A. Plana, Steve Temple, David R. Lester, René Schüffny, Steve B. Furber
2013 — conf
Live demonstration: Ethernet communication linking two large-scale neuromorphic systems.
ECCTD
Johannes Partzsch, Christian Mayr, Bernhard Vogginger, René Schüffny, Alexander D. Rast, Luis A. Plana, Steve B. Furber
2013 J jnl
Overview of the SpiNNaker System Architecture.
IEEE Trans. Computers
Steve B. Furber, David R. Lester, Luis A. Plana, Jim D. Garside, Eustace Painkras, Steve Temple, Andrew D. Brown
2013 C conf
Real-Time Interface Board for Closed-Loop Robotic Tasks on the SpiNNaker Neural Computing System.
ICANN
Christian Denk, Francisco Llobet-Blandino, Francesco Galluppi, Luis A. Plana, Steve B. Furber, Jörg Conradt
2013 J jnl
SpiNNaker: A 1-W 18-Core System-on-Chip for Massively-Parallel Neural Network Simulation.
IEEE J. Solid State Circuits
Eustace Painkras, Luis A. Plana, Jim D. Garside, Steve Temple, Francesco Galluppi, Cameron Patterson, David R. Lester, Andrew D. Brown, Steve B. Furber
2013 J jnl
SpiNNaker: Fault tolerance in a power- and area- constrained large-scale neuromimetic architecture.
Parallel Comput.
Javier Navaridas, Steve B. Furber, Jim D. Garside, Xin Jin, Mukaram M. Khan, David R. Lester, Mikel Luján, José Miguel-Alonso, Eustace Painkras, Cameron Patterson, Luis A. Plana, Alexander D. Rast, Dominic Richards, Yebin Shi, Steve Temple, Jian Wu, Shufan Yang
2012 — conf
A hierachical configuration system for a massively parallel neural hardware platform.
Conf. Computing Frontiers
Francesco Galluppi, Sergio Davies, Alexander D. Rast, Thomas Sharp, Luis A. Plana, Steve B. Furber
2012 — conf
An Asynchronous Fully Digital Delay Locked Loop for DDR SDRAM Data Recovery.
ASYNC
Jim D. Garside, Stephen B. Furber, Steve Temple, David M. Clark, Luis A. Plana
2012 — conf
Analytical Assessment of the Suitability of Multicast Communications for the SpiNNaker Neuromimetic System.
HPCC-ICESS
Javier Navaridas, Mikel Luján, Luis A. Plana, José Miguel-Alonso, Stephen B. Furber
2012 B conf
Event-driven MLP implementation on neuromimetic hardware.
IJCNN
Alexander D. Rast, Luis A. Plana, Stephen R. Welbourne, Stephen B. Furber
2012 J jnl
Managing Burstiness and Scalability in Event-Driven Models on the SpiNNaker Neuromimetic System.
Int. J. Parallel Program.
Alexander D. Rast, Javier Navaridas, Xin Jin, Francesco Galluppi, Luis A. Plana, José Miguel-Alonso, Cameron Patterson, Mikel Luján, Steve B. Furber
2012 J jnl
Scalable communications for a million-core neural processing architecture.
J. Parallel Distributed Comput.
Cameron Patterson, Jim D. Garside, Eustace Painkras, Steve Temple, Luis A. Plana, Javier Navaridas, Thomas Sharp, Steve B. Furber
2012 — conf
SpiNNaker: A multi-core System-on-Chip for massively-parallel neural net simulation.
CICC
Eustace Painkras, Luis A. Plana, Jim D. Garside, Steve Temple, Simon Davidson, Jeffrey Pepper, David M. Clark, Cameron Patterson, Steve B. Furber
2011 B conf
An event-driven model for the SpiNNaker virtual synaptic channel.
IJCNN
Alexander D. Rast, Francesco Galluppi, Sergio Davies, Luis A. Plana, Thomas Sharp, Steve B. Furber
2011 J jnl
Concurrent heterogeneous neural model simulation on real-time neuromimetic hardware.
Neural Networks
Alexander D. Rast, Francesco Galluppi, Sergio Davies, Luis A. Plana, Cameron Patterson, Thomas Sharp, David R. Lester, Steve B. Furber
2011 — conf
Event-Driven Simulation of Arbitrary Spiking Neural Networks on SpiNNaker.
ICONIP (3)
Thomas Sharp, Luis A. Plana, Francesco Galluppi, Steve B. Furber
2011 J jnl
Event-driven configuration of a neural network CMP system over an homogeneous interconnect fabric.
Parallel Comput.
Mukaram M. Khan, Alexander D. Rast, Javier Navaridas, X. Jin, Luis A. Plana, Mikel Luján, Steve Temple, Cameron Patterson, Dominic Richards, John V. Woods, José Miguel-Alonso, Stephen B. Furber
2011 J jnl
SpiNNaker: Design and Implementation of a GALS Multicore System-on-Chip.
ACM J. Emerg. Technol. Comput. Syst.
Luis A. Plana, David M. Clark, Simon Davidson, Steve B. Furber, Jim D. Garside, Eustace Painkras, Jeffrey Pepper, Steve Temple, John Bainbridge
2010 — conf
A communication infrastructure for a million processor machine.
Conf. Computing Frontiers
Andrew D. Brown, Steve B. Furber, Jeff S. Reeve, Peter R. Wilson, Mark Zwolinski, John E. Chad, Luis A. Plana, David R. Lester
2010 C conf
Algorithm for Mapping Multilayer BP Networks onto the SpiNNaker Neuromorphic Hardware.
ISPDC
Xin Jin, Mikel Luján, Muhammad Mukaram Khan, Luis A. Plana, Alexander D. Rast, Stephen R. Welbourne, Stephen B. Furber
2010 J jnl
Asynchronous Data-Driven Circuit Synthesis.
IEEE Trans. Very Large Scale Integr. Syst.
Sam Taylor, Doug A. Edwards, Luis A. Plana, Luis A. Tarazona
2010 C conf
Description-Level Optimisation of Synthesisable Asynchronous Circuits.
DSD
Luis A. Tarazona, Doug A. Edwards, Andrew Bardsley, Luis A. Plana
2010 — conf
Efficient parallel implementation of multilayer backpropagation networks on SpiNNaker.
Conf. Computing Frontiers
Xin Jin, Mikel Luján, Luis A. Plana, Alexander D. Rast, Stephen R. Welbourne, Steve B. Furber
2010 J jnl
Modeling Spiking Neural Networks on SpiNNaker.
Comput. Sci. Eng.
Xin Jin, Mikel Luján, Luis A. Plana, Sergio Davies, Steve Temple, Steve B. Furber
2010 — conf
Scalable event-driven native parallel processing: the SpiNNaker neuromimetic system.
Conf. Computing Frontiers
Alexander D. Rast, Xin Jin, Francesco Galluppi, Luis A. Plana, Cameron Patterson, Stephen B. Furber
2010 — conf
SpiNNaker: impact of traffic locality, causality and burstiness on the performance of the interconnection network.
Conf. Computing Frontiers
Javier Navaridas, Luis A. Plana, José Miguel-Alonso, Mikel Luján, Stephen B. Furber
2010 J jnl
System-on-Chip Design and Implementation.
IEEE Trans. Educ.
Linda E. M. Brackenbury, Luis A. Plana, Jeffrey Pepper
2009 C conf
A Synthesisable Quasi-Delay Insensitive Result Forwarding Unit for an Asynchronous Processor.
DSD
Luis A. Tarazona, Doug A. Edwards, Luis A. Plana
2009 J jnl
A Token-Managed Admission Control System for QoS Provision on a Best-Effort GALS Interconnect.
Fundam. Informaticae
Shufan Yang, Stephen B. Furber, Yebin Shi, Luis A. Plana
2009 B conf
A universal abstract-time platform for real-time neural networks.
IJCNN
Alexander D. Rast, Mukaram M. Khan, Xin Jin, Luis A. Plana, Steve B. Furber
2009 — conf
Adaptive admission control on the SpiNNaker MPSoC.
SoCC
Shufan Yang, Stephen B. Furber, Luis A. Plana
2009 C conf
Event-Driven Configuration of a Neural Network CMP System over a Homogeneous Interconnect Fabric.
ISPDC
Muhammad Mukaram Khan, Javier Navaridas, Alexander D. Rast, Xin Jin, Luis A. Plana, Mikel Luján, John V. Woods, José Miguel-Alonso, Steve B. Furber
2009 — conf
Fault Tolerant Delay Insensitive Inter-chip Communication.
ASYNC
Yebin Shi, Steve B. Furber, Jim D. Garside, Luis A. Plana
2009 A conf
Understanding the interconnection network of SpiNNaker.
ICS
Javier Navaridas, Mikel Luján, José Miguel-Alonso, Luis A. Plana, Steve B. Furber
2008 — conf
An On-Chip and Inter-Chip Communications Network for the SpiNNaker Massively-Parallel Neural Net Simulator.
NOCS
Luis A. Plana, John Bainbridge, Steve B. Furber, Sean Salisbury, Yebin Shi, Jian Wu
2008 — conf
An admission control system for QoS provision on a best-effort GALS interconnect.
ACSD
Shufan Yang, Steve B. Furber, Yebin Shi, Luis A. Plana
2008 — conf
Automatic Compilation of Data-Driven Circuits.
ASYNC
Sam Taylor, Doug A. Edwards, Luis A. Plana
2008 B conf
SpiNNaker: Mapping neural networks onto a massively-parallel chip multiprocessor.
IJCNN
Muhammad Mukaram Khan, David R. Lester, Luis A. Plana, Alexander D. Rast, Xin Jin, Eustace Painkras, Stephen B. Furber
2008 — conf
SpiNNaker: The Design Automation Problem.
ICONIP (2)
Andrew D. Brown, David R. Lester, Luis A. Plana, Steve B. Furber, Peter R. Wilson
2007 J jnl
A GALS Infrastructure for a Massively Parallel Multiprocessor.
IEEE Des. Test Comput.
Luis A. Plana, Stephen B. Furber, Steve Temple, Muhammad Mukaram Khan, Yebin Shi, Jian Wu, Shufan Yang
2007 Misc conf
Performance-driven syntax-directed synthesis of asynchronous processors.
CASES
Luis A. Plana, Doug A. Edwards, Sam Taylor, Luis A. Tarazona, Andrew Bardsley
2005 C conf
Attacking Control Overhead to Improve Synthesised Asynchronous Circuit Performance.
ICCD
Luis A. Plana, Sam Taylor, Doug A. Edwards
2004 A conf
The Design and Test of a Smartcard Chip Using a CHAIN Self-Timed Network-on-Chip.
DATE
W. J. Bainbridge, Luis A. Plana, Stephen B. Furber
2003 — conf
An Investigation into the Security of Self-Timed Circuits.
ASYNC
Z. C. Yu, Stephen B. Furber, Luis A. Plana
2003 J jnl
SPA - a secure Amulet core for smartcard applications.
Microprocess. Microsystems
Luis A. Plana, Peter A. Riocreux, W. J. Bainbridge, Andrew Bardsley, Steve Temple, Jim D. Garside, Z. C. Yu
2002 — conf
SPA - A Synthesisable Amulet Core for Smartcard pplications.
ASYNC
W. J. Bainbridge, Andrew Bardsley, Steve Temple, Jim D. Garside, Peter A. Riocreux, Luis A. Plana
1998 J jnl
Architectural optimization for low-power nonpipelined asynchronous systems.
IEEE Trans. Very Large Scale Integr. Syst.
Luis A. Plana, Steven M. Nowick
1998 C conf
Pulse-mode macromodular systems.
ICCD
Luis A. Plana, Stephen H. Unger
1996 A conf
Concurrency-oriented optimization for low-power asynchronous systems.
ISLPED
Luis A. Plana, Steven M. Nowick