Luis A. Camuñas-Mesa

43 papers A 2B 1C 12Journal 18Unranked 10
YearRankTypeTitle / Venue / Authors
2025 J jnl
BAM-SLDK: biologically inspired attention mechanism with spiking learnable delayed kernel synapses.
Neuromorph. Comput. Eng.
Mario Chacón-Falcón, Alberto Patiño-Saucedo, Luis A. Camuñas-Mesa, Teresa Serrano-Gotarredona, Bernabé Linares-Barranco
2025 C conf
New self-calibration algorithm for programmable multi-core memristor-CMOS chip for neuromorphic computing.
ISCAS
Iván Díez de los Ríos, Luis A. Camuñas-Mesa, Teresa Serrano-Gotarredona, Bernabé Linares-Barranco
2025 — conf
Three Decades of IMSE Neuromorphic Group.
DCIS
Bernabé Linares-Barranco, Luis A. Camuñas-Mesa, Teresa Serrano-Gotarredona
2024 J jnl
A Fully Digital Relaxation-Aware Analog Programming Technique for HfOx RRAM Arrays.
IEEE Trans. Circuits Syst. II Express Briefs
Hamid Reza Erfani Jazi, Luis A. Camuñas-Mesa, Elisa Vianello, Teresa Serrano-Gotarredona, Bernabé Linares-Barranco
2024 C conf
Mismatch calibration strategy for query-driven AER read-out in a memristor-CMOS neuromorphic chip.
ISCAS
Luis A. Camuñas-Mesa, Teresa Serrano-Gotarredona, Bernabé Linares-Barranco
2023 J jnl
A Fully Digital Relaxation-Aware Analog Programming Technique for HfOx RRAM Arrays.
CoRR
Hamid Reza Erfani Jazi, Luis A. Camuñas-Mesa, Elisa Vianello, Teresa Serrano-Gotarredona, Bernabé Linares-Barranco
2023 C conf
A multi-core memristor chip for Stochastic Binary STDP.
ISCAS
Ivan Diez-de-los-Rios, Luis A. Camuñas-Mesa, Elisa Vianello, Carlo Reita, Teresa Serrano-Gotarredona, Bernabé Linares-Barranco
2023 J jnl
Combining Software-Defined Radio Learning Modules and Neural Networks for Teaching Communication Systems Courses.
Inf.
Luis A. Camuñas-Mesa, José M. de la Rosa
2023 J jnl
Compact Functional Testing for Neuromorphic Computing Circuits.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Sarah A. El-Sayed, Theofilos Spyrou, Luis A. Camuñas-Mesa, Haralampos-G. Stratigopoulos
2023 — conf
Study of foveation mechanisms in Dynamic Vision Sensors.
DCIS
Isabel Ortíz-Ramírez, Luis A. Camuñas-Mesa, Bernabé Linares-Barranco, Teresa Serrano-Gotarredona
2023 J jnl
Using ANNs to predict the evolution of spectrum occupancy in cognitive-radio systems.
Integr.
Promise I. Enwere, Encarnación Cervantes-Requena, Luis A. Camuñas-Mesa, José M. de la Rosa
2022 J jnl
A CMOL-Like Memristor-CMOS Neuromorphic Chip-Core Demonstrating Stochastic Binary STDP.
CoRR
Luis A. Camuñas-Mesa, Elisa Vianello, Carlo Reita, Teresa Serrano-Gotarredona, Bernabé Linares-Barranco
2022 J jnl
A CMOL-Like Memristor-CMOS Neuromorphic Chip-Core Demonstrating Stochastic Binary STDP.
IEEE J. Emerg. Sel. Topics Circuits Syst.
Luis A. Camuñas-Mesa, Elisa Vianello, Carlo Reita, Teresa Serrano-Gotarredona, Bernabé Linares-Barranco
2022 A conf
Reliability Analysis of a Spiking Neural Network Hardware Accelerator.
DATE
Theofilos Spyrou, Sarah A. El-Sayed, Engin Afacan, Luis A. Camuñas-Mesa, Bernabé Linares-Barranco, Haralampos-G. Stratigopoulos
2022 — conf
Using ANNs to Predict Frequency Spectrum Occupancy in Cognitive-Radio Receivers.
DCIS
Promise I. Okorie, Luis A. Camuñas-Mesa, José M. de la Rosa
2021 C conf
Cognitive Radio Circuits and Systems - Application to Digitizers.
ISCAS
Hassan Aboushady, Alhassan Sayed, Luis A. Camuñas-Mesa, José M. de la Rosa
2021 J jnl
Experimental Body-input Three-stage DC offset Calibration Scheme for Memristive Crossbar.
CoRR
Charanraj Mohan, Luis A. Camuñas-Mesa, Elisa Vianello, Carlo Reita, José M. de la Rosa, Teresa Serrano-Gotarredona, Bernabé Linares-Barranco
2021 C conf
Implementation of Binary Stochastic STDP Learning Using Chalcogenide-Based Memristive Devices.
ISCAS
C. Mohan, Luis A. Camuñas-Mesa, José M. de la Rosa, Teresa Serrano-Gotarredona, Bernabé Linares-Barranco
2021 J jnl
Implementation of binary stochastic STDP learning using chalcogenide-based memristive devices.
CoRR
C. Mohan, Luis A. Camuñas-Mesa, José M. de la Rosa, Teresa Serrano-Gotarredona, Bernabé Linares-Barranco
2021 J jnl
Neuromorphic Low-Power Inference on Memristive Crossbars With On-Chip Offset Calibration.
IEEE Access
Charanraj Mohan, Luis A. Camuñas-Mesa, José M. de la Rosa, Elisa Vianello, Teresa Serrano-Gotarredona, Bernabé Linares-Barranco
2021 A conf
Neuron Fault Tolerance in Spiking Neural Networks.
DATE
Theofilos Spyrou, Sarah A. El-Sayed, Engin Afacan, Luis A. Camuñas-Mesa, Bernabé Linares-Barranco, Haralampos-G. Stratigopoulos
2020 C conf
Experimental Body-Input Three-Stage DC Offset Calibration Scheme for Memristive Crossbar.
ISCAS
Charanraj Mohan, Luis A. Camuñas-Mesa, Elisa Vianello, Carlo Reita, José M. de la Rosa, Teresa Serrano-Gotarredona, Bernabé Linares-Barranco
2020 — conf
Implementation of a tunable spiking neuron for STDP with memristors in FDSOI 28nm.
AICAS
Luis A. Camuñas-Mesa, Bernabé Linares-Barranco, Teresa Serrano-Gotarredona
2020 C conf
Lessons Learned the Hard Way.
ISCAS
Tobi Delbruck, Ibrahim Abe M. Elfadel, Shahzad Muzaffar, Germain Haessig, Bo Wang, Amine Bermak, Rui Graca, Luis A. Camuñas-Mesa, Bathiya Senevirathna, Pamela Abshire, Bernabé Linares-Barranco, Saeed Afshar, Shih-Chii Liu, Runchun Mark Wang, Piotr Dudek, Stephen J. Carey, José M. de la Rosa, Marc Dandin, Sheung Lu, Vincent Frick, Teresa Serrano-Gotarredona, Paula López, Melika Payvand, Advait Madhavan, Eric R. Fossum, Juan Camilo Vasquez Tieck, Ian Williams, Yan Liu, Timothy G. Constandinou, Alexander Serb, Ricardo Carmona-Galán, Robert Nawrocki, Walter D. Leon-Salas
2020 — conf
Low Order Wideband Multiplierless Comb Compensator.
MWSCAS
Gordana Jovanovic-Dolecek, Luis A. Camuñas-Mesa, José M. de la Rosa
2020 C conf
Spiking Neuron Hardware-Level Fault Modeling.
IOLTS
Sarah A. El-Sayed, Theofilos Spyrou, Antonios Pavlidis, Engin Afacan, Luis A. Camuñas-Mesa, Bernabé Linares-Barranco, Haralampos-G. D. Stratigopoulos
2020 — conf
Using Neural Networks for Optimum band selection in Cognitive-Radio Systems.
ICECS
Virginia Zúñiga-González, Luis A. Camuñas-Mesa, Bernabé Linares-Barranco, Teresa Serrano-Gotarredona, José M. de la Rosa
2019 — conf
Low-power hardware implementation of SNN with decision block for recognition tasks.
ICECS
Luis A. Camuñas-Mesa, Bernabé Linares-Barranco, Teresa Serrano-Gotarredona
2019 — conf
Self-Testing Analog Spiking Neuron Circuit.
SMACD
Sarah A. El-Sayed, Luis A. Camuñas-Mesa, Bernabé Linares-Barranco, Haralampos-G. D. Stratigopoulos
2018 C conf
Event-Driven Configurable Module with Refractory Mechanism for ConvNets on FPGA.
ISCAS
Luis A. Camuñas-Mesa, Y. Domínguez-Cordero, Teresa Serrano-Gotarredona, Bernabé Linares-Barranco
2018 J jnl
Event-Driven Stereo Visual Tracking Algorithm to Solve Object Occlusion.
IEEE Trans. Neural Networks Learn. Syst.
Luis A. Camuñas-Mesa, Teresa Serrano-Gotarredona, Sio-Hoi Ieng, Ryad Benosman, Bernabé Linares-Barranco
2014 — conf
Event-driven sensing and processing for high-speed robotic vision.
BioCAS
Luis A. Camuñas-Mesa, Teresa Serrano-Gotarredona, Bernabé Linares-Barranco
2014 C conf
Event-driven stereo vision with orientation filters.
ISCAS
Luis A. Camuñas-Mesa, Teresa Serrano-Gotarredona, Bernabé Linares-Barranco, Sio-Hoi Ieng, Ryad Benosman
2014 — conf
Live demonstration: Event-driven sensing and processing for high-speed robotic vision.
BioCAS
Luis A. Camuñas-Mesa, Teresa Serrano-Gotarredona, Bernabé Linares-Barranco
2013 J jnl
A Detailed and Fast Model of Extracellular Recordings.
Neural Comput.
Luis A. Camuñas-Mesa, Rodrigo Quian Quiroga
2012 J jnl
An Event-Driven Multi-Kernel Convolution Processor Module for Event-Driven Vision Sensors.
IEEE J. Solid State Circuits
Luis A. Camuñas-Mesa, Carlos Zamarreño-Ramos, Alejandro Linares-Barranco, Antonio Acosta-Jimenez, Teresa Serrano-Gotarredona, Bernabé Linares-Barranco
2011 J jnl
A 32, times, 32 Pixel Convolution Processor Chip for Address Event Vision Sensors With 155 ns Event Latency and 20 Meps Throughput.
IEEE Trans. Circuits Syst. I Regul. Pap.
Luis A. Camuñas-Mesa, Antonio Acosta-Jimenez, Carlos Zamarreño-Ramos, Teresa Serrano-Gotarredona, Bernabé Linares-Barranco
2010 J jnl
Fast vision through frameless event-based sensing and convolutional processing: application to texture recognition.
IEEE Trans. Neural Networks
José Antonio Pérez-Carrasco, Begoña Acha, Carmen Serrano, Luis A. Camuñas-Mesa, Teresa Serrano-Gotarredona, Bernabé Linares-Barranco
2010 B conf
Neocortical frame-free vision sensing and processing through scalable Spiking ConvNet hardware.
IJCNN
Luis A. Camuñas-Mesa, José Antonio Pérez-Carrasco, Carlos Zamarreño-Ramos, Teresa Serrano-Gotarredona, Bernabé Linares-Barranco
2010 C conf
On scalable spiking convnet hardware for cortex-like visual sensory processing systems.
ISCAS
Luis A. Camuñas-Mesa, José Antonio Pérez-Carrasco, Carlos Zamarreño-Ramos, Teresa Serrano-Gotarredona, Bernabé Linares-Barranco
2009 J jnl
CAVIAR: A 45k Neuron, 5M Synapse, 12G Connects/s AER Hardware Sensory-Processing- Learning-Actuating System for High-Speed Visual Object Recognition and Tracking.
IEEE Trans. Neural Networks
Rafael Serrano-Gotarredona, Matthias Oster, Patrick Lichtsteiner, Alejandro Linares-Barranco, Rafael Paz-Vicente, Francisco Gomez-Rodriguez, Luis A. Camuñas-Mesa, Raphael Berner, Manuel Rivas Pérez, Tobi Delbruck, Shih-Chii Liu, Rodney J. Douglas, Philipp Häfliger, Gabriel Jiménez-Moreno, Antón Civit Balcells, Teresa Serrano-Gotarredona, Antonio Acosta-Jimenez, Bernabé Linares-Barranco
2008 C conf
Fully digital AER convolution chip for vision processing.
ISCAS
Luis A. Camuñas-Mesa, Antonio Acosta-Jimenez, Teresa Serrano-Gotarredona, Bernabé Linares-Barranco
2007 J jnl
The Stochastic I-Pot: A Circuit Block for Programming Bias Currents.
IEEE Trans. Circuits Syst. II Express Briefs
Rafael Serrano-Gotarredona, Luis A. Camuñas-Mesa, Teresa Serrano-Gotarredona, Juan A. Leñero-Bardallo, Bernabé Linares-Barranco