Luigi Dilillo - RankMe

145 papers A* 2A 15B 15C 17Misc 7Journal 25Unranked 62

Year	Rank	Type	Title / Venue / Authors
2026	—	`conf`	Characterization of a Fault-Tolerant RISC-V SoC in an SRAM-based FPGA Under Proton Irradiation. LATS Wesley Grignani, Douglas A. dos Santos, Carolina Imianosky, Douglas R. Melo, Frédéric Wrobel, Luigi Dilillo
2026	—	`conf`	Design and Reliability Analysis of a Pipeline RISC-V Processor Core. LATS Douglas A. dos Santos, Wesley Grignani, Carolina Imianosky, Douglas R. Melo, Luigi Dilillo
2026	—	`conf`	Resilience Analysis of a Fault-Tolerant MPSoC Interconnection Architecture Under SEU Fault Injection. LATS Thiago H. Rausch, Wesley Grignani, Luigi Dilillo, Douglas R. Melo
2025	J	`jnl`	A Dependable and Low-Cost CCSDS 123 Hyperspectral Image Compressor. IEEE Embed. Syst. Lett. Wesley Grignani, Douglas A. dos Santos, Felipe Viel, Luigi Dilillo, Douglas R. Melo
2025	J	`jnl`	A fault-tolerant CCSDS 123 hardware accelerator for space applications. Integr. Wesley Grignani, Felipe Viel, Douglas A. dos Santos, Luigi Dilillo, Douglas R. Melo
2025	—	`conf`	Compact SER Models for Line-Source-Induced Charge Collection Using Model Order Reduction. DFT Pavlos Stoikos, Olympia Axelou, Pelopidas Tsoumanis, Georgios Ioannis Paliaroutis, Luigi Dilillo, Anuj Pathania, George Floros
2025	—	`conf`	Efficient TinyML Inference on a Fault-Tolerant RISC-V SoC with Vector Extension. IWASI Carolina Imianosky, Douglas A. dos Santos, Luigi Dilillo
2025	—	`conf`	Hardening an AMBA-AXI Network Interface for a Reliable Network-on-Chip. LASCAS Thiago H. Rausch, Wesley Grignani, Gustavo H. S. Müller, Douglas A. dos Santos, Luigi Dilillo, Douglas R. Melo
2025	A	`conf`	Multi-Partner Project: Twinning for Excellence in Reliable Electronics (TWIN-RELECT). DATE Marko S. Andjelkovic, Fabian Vargas, Milos Krstic, Luigi Dilillo, Alain Michez, Frederic Wrobel, Davide Bertozzi, Mikel Luján, Christos Georgakidis, Nikolaos Chatzivangelis, Katerina Tsilingiri, Nikolaos Zazatis, Georgios Ioannis Paliaroutis, Pelopidas Tsoumanis, Christos P. Sotiriou
2025	J	`jnl`	Reliability Analysis of Baremetal and FreeRTOS Applications on Microchip PolarFire SoC RISC-V Multiprocessors Using High-Energy Protons. IEEE Access André Martins Pio de Mattos, Douglas A. dos Santos, Luigi Dilillo
2025	—	`conf`	Reliability and Performance Evaluation of a Fault-Tolerant MPSoC Interconnection Architecture. DFT Thiago H. Rausch, Wesley Grignani, Luigi Dilillo, Douglas R. Melo
2025	—	`conf`	Special Session Paper: Simulation Methodologies and Experiments for Reliability Analysis of Devices in Radiation Harsh Environments. DFT Nikolaos Chatzivangelis, Nikolaos Zazatis, Wesley Grignani, Georgios Ioannis Paliaroutis, Douglas A. dos Santos, Carolina Imianosky, Maria Kastriotou, Carlo Cazzaniga, Frédéric Wrobel, Alessandro Veronesi, Christos P. Sotiriou, Marko S. Andjelkovic, Fabian Luis Vargas, Davide Bertozzi, Luigi Dilillo
2024	—	`conf`	Implementation and Reliability Evaluation of a ChaCha20 Stream Cipher Hardware Accelerator. DFT Wesley Grignani, Khalil G. Queiroz de Santana, Douglas A. dos Santos, Luigi Dilillo, Douglas R. Melo
2024	—	`conf`	Reliability Analysis of a Low-Cost CCSDS 123 Hyperspectral Image Compressor. DFT Wesley Grignani, Douglas A. dos Santos, Luigi Dilillo, Douglas R. Melo
2024	—	`conf`	Special Session: Reliability and Performance Evaluation of a RISC-V Vector Extension Unit for Vector Multiplication. DFT Carolina Imianosky, Douglas A. dos Santos, Douglas R. Melo, Felipe Viel, Luigi Dilillo
2023	—	`conf`	A Low-Cost Hardware Accelerator for CCSDS 123 Lossless Hyperspectral Image Compression. DFT Wesley Grignani, Douglas A. dos Santos, Luigi Dilillo, Felipe Viel, Douglas R. Melo
2023	J	`jnl`	A Survey on Deep Learning Resilience Assessment Methodologies. Computer Annachiara Ruospo, Ernesto Sánchez, Lucas Matana Luza, Luigi Dilillo, Marcello Traiola, Alberto Bosio
2023	—	`conf`	Characterization of a Fault-Tolerant RISC-V System-on-Chip for Space Environments. DFT Douglas A. dos Santos, André Martins Pio de Mattos, Douglas R. Melo, Luigi Dilillo
2023	—	`conf`	Hardening a Real-Time Operating System for a Dependable RISC-V System-on-Chip. DFT Benjamin W. Mezger, Douglas A. dos Santos, Luigi Dilillo, Douglas R. Melo
2023	—	`conf`	Implementation and Reliability Evaluation of a RISC-V Vector Extension Unit. DFT Carolina Imianosky, Douglas A. dos Santos, Douglas R. Melo, Felipe Viel, Luigi Dilillo
2023	—	`conf`	Using HARV-SoC for Reliable Sensing Applications in Radiation Harsh Environments. IWASI André Martins Pio de Mattos, Douglas A. dos Santos, Carolina Imianosky, Douglas R. Melo, Luigi Dilillo
2022	J	`jnl`	A Survey of the RISC-V Architecture Software Support. IEEE Access Benjamin W. Mezger, Douglas A. dos Santos, Luigi Dilillo, Cesar A. Zeferino, Douglas R. Melo
2022	J	`jnl`	Emulating the Effects of Radiation-Induced Soft-Errors for the Reliability Assessment of Neural Networks. IEEE Trans. Emerg. Top. Comput. Lucas Matana Luza, Annachiara Ruospo, Daniel Söderström, Carlo Cazzaniga, Maria Kastriotou, Ernesto Sánchez, Alberto Bosio, Luigi Dilillo
2022	B	`conf`	Impact of Atmospheric and Space Radiation on Sensitive Electronic Devices. ETS Lucas Matana Luza, Frederic Wrobel, Luis Entrena, Luigi Dilillo
2022	—	`conf`	Neutron Irradiation Testing and Analysis of a Fault-Tolerant RISC-V System-on-Chip. DFT Douglas A. dos Santos, André Martins Pio de Mattos, Lucas M. Luza, Carlo Cazzaniga, Maria Kastriotou, Douglas R. Melo, Luigi Dilillo
2021	—	`ed.`	36th IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, DFT 2021, Athens, Greece, October 6-8, 2021 DFT Luigi Dilillo, Luca Cassano, Athanasios Papadimitriou
2021	C	`conf`	A Model-Based Framework to Assess the Reliability of Safety-Critical Applications. DDECS Lucas Matana Luza, Annachiara Ruospo, Alberto Bosio, Ernesto Sánchez, Luigi Dilillo
2021	—	`conf`	Characterization of a RISC-V System-on-Chip under Neutron Radiation. DTIS Douglas A. dos Santos, Lucas M. Luza, Maria Kastriotou, Carlo Cazzaniga, Cesar A. Zeferino, Douglas R. Melo, Luigi Dilillo
2021	—	`conf`	Design and Evaluation of Implementation Impact on a Fault-Tolerant Network-on-Chip Router. DTIS Douglas Rossi Melo, César Albenes Zeferino, Eduardo Augusto Bezerra, Luigi Dilillo
2021	—	`conf`	Pros and Cons of Fault Injection Approaches for the Reliability Assessment of Deep Neural Networks. LATS Annachiara Ruospo, Lucas Matana Luza, Alberto Bosio, Marcello Traiola, Luigi Dilillo, Ernesto Sánchez
2021	—	`conf`	Technology Impact on Neutron-Induced Effects in SDRAMs: A Comparative Study. DTIS Lucas Matana Luza, Daniel Söderström, André Martins Pio de Mattos, Eduardo Augusto Bezerra, Carlo Cazzaniga, Maria Kastriotou, Christian Poivey, Luigi Dilillo
2020	—	`conf`	A Low-Cost Fault-Tolerant RISC-V Processor for Space Systems. DTIS Douglas Almeida dos Santos, Lucas Matana Luza, César Albenes Zeferino, Luigi Dilillo, Douglas Rossi de Melo
2020	—	`conf`	Effects of Thermal Neutron Irradiation on a Self-Refresh DRAM. DTIS Lucas Matana Luza, Daniel Söderström, Helmut Puchner, Rubén García Alía, Manon Letiche, Alberto Bosio, Luigi Dilillo
2020	—	`ed.`	IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, DFT 2020, Frascati, Italy, October 19-21, 2020 DFT Luigi Dilillo, Mihalis Psarakis, Taniya Siddiqua
2020	—	`conf`	Investigating the Impact of Radiation-Induced Soft Errors on the Reliability of Approximate Computing Systems. DFT Lucas Matana Luza, Daniel Söderström, Georgios Tsiligiannis, Helmut Puchner, Carlo Cazzaniga, Ernesto Sánchez, Alberto Bosio, Luigi Dilillo
2019	—	`conf`	A Fault-Tolerant Reconfigurable Platform for Communication Modules of Satellites. LATS Cezar Antônio Rigo, Lucas M. Luza, Elder Dominghini Tramontin, Victor M. Goncalves Martins, Sara Vega Martínez, Leonardo Kessler Slongo, Laio Oriel Seman, Luigi Dilillo, Fabian Luis Vargas, Eduardo A. Bezerra
2019	—	`conf`	Analyzing the Error Propagation in a Parameterizable Network-on-Chip Router. LATS Douglas Rossi de Melo, César Albenes Zeferino, Luigi Dilillo, Eduardo Augusto Bezerra
2019	—	`conf`	Characterization of a RISC-V Microcontroller Through Fault Injection. ApplePies Dario Asciolla, Luigi Dilillo, Douglas A. dos Santos, Douglas R. Melo, Alessandra Menicucci, Marco Ottavi
2019	—	`conf`	Design and Implementation of a Flexible Interface for TID Detector. IWASI Iacopo Fara, Lucas Matana Luza, Jérôme Boch, Gianluca Furano, Marco Ottavi, Luigi Dilillo
2019	—	`conf`	Effects of Heavy Ion and Proton Irradiation on a SLC NAND Flash Memory. DFT Lucas Matana Luza, Alexandre Besser, Viyas Gupta, Arto Javanainen, Ali Mohammadzadeh, Luigi Dilillo
2019	J	`jnl`	Maximizing the Inner Resilience of a Network-on-Chip through Router Controllers Design. Sensors Douglas R. Melo, Cesar A. Zeferino, Luigi Dilillo, Eduardo A. Bezerra
2018	—	`conf`	Evaluation of the temperature influence on SEU vulnerability of DICE and 6T-SRAM cells. DTIS Emna Farjallah, Valentin Gherman, Jean-Marc Armani, Luigi Dilillo
2017	J	`jnl`	A calculation method to estimate single event upset cross section. Microelectron. Reliab. Frederic Wrobel, Antoine D. Touboul, Vincent Pouget, Luigi Dilillo, Jerome Boch, Frédéric Saigné
2017	A	`conf`	Improvement of the tolerated raw bit error rate in NAND flash-based SSDs with the help of embedded statistics. ITC Valentin Gherman, Emna Farjallah, Jean-Marc Armani, Marcelino Seif, Luigi Dilillo
2017	B	`conf`	Refresh frequency reduction of data stored in SSDs based on A-timer and timestamps. ETS Marcelino Seif, Emna Farjallah, Franck Badets, Emna Chabchoub, Christophe Layer, Jean-Marc Armani, Francis Joffre, Costin Anghel, Luigi Dilillo, Valentin Gherman
2016	—	`conf`	An effective BIST architecture for power-gating mechanisms in low-power SRAMs. ISQED Alberto Bosio, Luigi Dilillo, Patrick Girard, Arnaud Virazel, Leonardo Bonet Zordan
2016	J	`jnl`	Design for Test and Diagnosis of Power Switches. J. Circuits Syst. Comput. Miroslav Valka, Alberto Bosio, Luigi Dilillo, Patrick Girard, Arnaud Virazel, Philippe Debaud, Stephane Guilhot
2015	—	`conf`	An ATPG Flow to Generate Crosstalk-Aware Path Delay Pattern. ISVLSI Anu Asokan, Alberto Bosio, Arnaud Virazel, Luigi Dilillo, Patrick Girard, Serge Pravossoudovitch
2015	—	`conf`	An effective ATPG flow for Gate Delay Faults. DTIS Alberto Bosio, Luigi Dilillo, Patrick Girard, Arnaud Virazel, Paolo Bernardi, Matteo Sonza Reorda
2015	B	`conf`	An effective hybrid fault-tolerant architecture for pipelined cores. ETS Imran Wali, Arnaud Virazel, Alberto Bosio, Luigi Dilillo, Patrick Girard
2015	C	`conf`	Design-for-Diagnosis Architecture for Power Switches. DDECS Miroslav Valka, Alberto Bosio, Luigi Dilillo, Patrick Girard, Arnaud Virazel, P. Debaud, S. Guilhot
2015	A	`conf`	Exploring the impact of functional test programs re-used for power-aware testing. DATE Aymen Touati, Alberto Bosio, Luigi Dilillo, Patrick Girard, Arnaud Virazel, Paolo Bernardi, Matteo Sonza Reorda
2015	—	`conf`	Real-time SRAM based particle detector. IWASI Luigi Dilillo, Alexandre Bosser, Viyas Gupta, Frederic Wrobel, Frédéric Saigné
2015	—	`conf`	Scan-chain intra-cell defects grading. DTIS Aymen Touati, Alberto Bosio, Luigi Dilillo, Patrick Girard, Arnaud Virazel, Paolo Bernardi, Matteo Sonza Reorda
2014	J	`jnl`	A Complete Resistive-Open Defect Analysis for Thermally Assisted Switching MRAMs. IEEE Trans. Very Large Scale Integr. Syst. Joao Azevedo, Arnaud Virazel, Alberto Bosio, Luigi Dilillo, Patrick Girard, Aida Todri-Sanial, Jérémy Alvarez-Herault, Ken Mackay
2014	—	`conf`	A Comprehensive Evaluation of Functional Programs for Power-Aware Test. NATW Aymen Touati, Alberto Bosio, Luigi Dilillo, Patrick Girard, Aida Todri-Sanial, Arnaud Virazel, Paolo Bernardi
2014	—	`conf`	A Delay Probability Metric for Input Pattern Ranking Under Process Variation and Supply Noise. ISVLSI Anu Asokan, Aida Todri-Sanial, Alberto Bosio, Luigi Dilillo, Patrick Girard, Serge Pravossoudovitch, Arnaud Virazel
2014	J	`jnl`	A New Hybrid Fault-Tolerant Architecture for Digital CMOS Circuits and Systems. J. Electron. Test. D. A. Tran, Arnaud Virazel, Alberto Bosio, Luigi Dilillo, Patrick Girard, Serge Pravossoudovitch, Hans-Joachim Wunderlich
2014	C	`conf`	An intra-cell defect grading tool. DDECS Alberto Bosio, Luigi Dilillo, Patrick Girard, Aida Todri-Sanial, Arnaud Virazel, S. Bernabovi, Paolo Bernardi
2014	J	`jnl`	Globally Constrained Locally Optimized 3-D Power Delivery Networks. IEEE Trans. Very Large Scale Integr. Syst. Aida Todri-Sanial, Sandip Kundu, Patrick Girard, Alberto Bosio, Luigi Dilillo, Arnaud Virazel
2014	J	`jnl`	Intra-Cell Defects Diagnosis. J. Electron. Test. Zhenzhou Sun, Alberto Bosio, Luigi Dilillo, Patrick Girard, Serge Pravossoudovitch, Arnaud Virazel, Etienne Auvray
2014	—	`conf`	On the Generation of Diagnostic Test Set for Intra-cell Defects. ATS Zhenzhou Sun, Alberto Bosio, Luigi Dilillo, Patrick Girard, Arnaud Virazel, Etienne Auvray
2014	J	`jnl`	On the Test and Mitigation of Malfunctions in Low-Power SRAMs. J. Electron. Test. Leonardo Bonet Zordan, Alberto Bosio, Luigi Dilillo, Patrick Girard, Arnaud Virazel, Nabil Badereddine
2014	C	`conf`	Path delay test in the presence of multi-aggressor crosstalk, power supply noise and ground bounce. DDECS Anu Asokan, Aida Todri-Sanial, Alberto Bosio, Luigi Dilillo, Patrick Girard, Serge Pravossoudovitch, Arnaud Virazel
2014	—	`conf`	Power supply noise-aware workload assignments for homogeneous 3D MPSoCs with thermal consideration. ASP-DAC Yuanqing Cheng, Aida Todri-Sanial, Alberto Bosio, Luigi Dilillo, Patrick Girard, Arnaud Virazel
2014	C	`conf`	Protecting combinational logic in pipelined microprocessor cores against transient and permanent faults. DDECS Imran Wali, Arnaud Virazel, Alberto Bosio, Luigi Dilillo, Patrick Girard, Aida Todri
2014	Misc	`conf`	TSV aware timing analysis and diagnosis in paths with multiple TSVs. VTS Carolina Metzler, Aida Todri-Sanial, Alberto Bosio, Luigi Dilillo, Patrick Girard, Arnaud Virazel
2014	C	`conf`	Test and diagnosis of power switches. DDECS Miroslav Valka, Alberto Bosio, Luigi Dilillo, Aida Todri, Arnaud Virazel, Patrick Girard, P. Debaud, S. Guilhot
2014	C	`conf`	Timing-aware ATPG for critical paths with multiple TSVs. DDECS Carolina Metzler, Aida Todri-Sanial, Alberto Bosio, Luigi Dilillo, Patrick Girard, Arnaud Virazel
2014	B	`conf`	iBoX - Jitter based Power Supply Noise sensor. ETS Miroslav Valka, Alberto Bosio, Luigi Dilillo, Aida Todri, Arnaud Virazel, Patrick Girard, P. Debaud, S. Guilhot
2013	J	`jnl`	A Study of Tapered 3-D TSVs for Power and Thermal Integrity. IEEE Trans. Very Large Scale Integr. Syst. Aida Todri, Sandip Kundu, Patrick Girard, Alberto Bosio, Luigi Dilillo, Arnaud Virazel
2013	Misc	`conf`	A built-in scheme for testing and repairing voltage regulators of low-power srams. VTS Leonardo Bonet Zordan, Alberto Bosio, Luigi Dilillo, Patrick Girard, Aida Todri, Arnaud Virazel, Nabil Badereddine
2013	—	`conf`	Adaptive Source Bias for Improved Resistive-Open Defect Coverage during SRAM Testing. Asian Test Symposium Elena I. Vatajelu, Luigi Dilillo, Alberto Bosio, Patrick Girard, Aida Todri, Arnaud Virazel, Nabil Badereddine
2013	B	`conf`	Analyzing resistive-open defects in SRAM core-cell under the effect of process variability. ETS Elena I. Vatajelu, Alberto Bosio, Luigi Dilillo, Patrick Girard, Aida Todri, Arnaud Virazel, Nabil Badereddine
2013	—	`conf`	Analyzing the effect of concurrent variability in the core cells and sense amplifiers on SRAM read access failures. DTIS Elena I. Vatajelu, Alberto Bosio, Luigi Dilillo, Patrick Girard, Aida Todri, Arnaud Virazel, Nabil Badereddine
2013	—	`conf`	Characterization of an SRAM based particle detector for mixed-field radiation environments. IWASI Georgios Tsiligiannis, Luigi Dilillo, Alberto Bosio, Patrick Girard, Serge Pravossoudovitch, Aida Todri-Sanial, Arnaud Virazel, Julien Mekki, Markus Brugger, J.-R. Vaillé, Frederic Wrobel, Frédéric Saigné
2013	B	`conf`	Computing detection probability of delay defects in signal line tsvs. ETS Carolina Metzler, Aida Todri-Sanial, Alberto Bosio, Luigi Dilillo, Patrick Girard, Arnaud Virazel, Pascal Vivet, Marc Belleville
2013	—	`conf`	Effect-cause intra-cell diagnosis at transistor level. ISQED Zhenzhou Sun, Alberto Bosio, Luigi Dilillo, Patrick Girard, Aida Todri, Arnaud Virazel, Etienne Auvray
2013	J	`jnl`	Fast Power Evaluation for Effective Generation of Test Programs Maximizing Peak Power Consumption. J. Low Power Electron. Paolo Bernardi, Mauricio de Carvalho, Ernesto Sánchez, Matteo Sonza Reorda, Alberto Bosio, Luigi Dilillo, Miroslav Valka, Patrick Girard
2013	—	`conf`	On the correlation between Static Noise Margin and Soft Error Rate evaluated for a 40nm SRAM cell. DFTS Elena I. Vatajelu, Georgios Tsiligiannis, Luigi Dilillo, Alberto Bosio, Patrick Girard, Serge Pravossoudovitch, Aida Todri, Arnaud Virazel, Frederic Wrobel, Frédéric Saigné
2013	A	`conf`	On the reuse of read and write assist circuits to improve test efficiency in low-power SRAMs. ITC Leonardo Bonet Zordan, Alberto Bosio, Luigi Dilillo, Patrick Girard, Aida Todri, Arnaud Virazel, Nabil Badereddine
2013	C	`conf`	SRAM soft error rate evaluation under atmospheric neutron radiation and PVT variations. IOLTS Georgios Tsiligiannis, Elena I. Vatajelu, Luigi Dilillo, Alberto Bosio, Patrick Girard, Serge Pravossoudovitch, Aida Todri, Arnaud Virazel, Frederic Wrobel, Frédéric Saigné
2013	A	`conf`	Test solution for data retention faults in low-power SRAMs. DATE Leonardo Bonet Zordan, Alberto Bosio, Luigi Dilillo, Patrick Girard, Aida Todri, Arnaud Virazel, Nabil Badereddine
2013	J	`jnl`	Uncorrelated Power Supply Noise and Ground Bounce Consideration for Test Pattern Generation. IEEE Trans. Very Large Scale Integr. Syst. Aida Todri, Alberto Bosio, Luigi Dilillo, Patrick Girard, Arnaud Virazel
2013	—	`conf`	Worst-case power supply noise and temperature distribution analysis for 3D PDNs with multiple clock domains. NEWCAS Aida Todri-Sanial, Alberto Bosio, Luigi Dilillo, Patrick Girard, Serge Pravossoudovitch, Arnaud Virazel
2012	Misc	`conf`	A pseudo-dynamic comparator for error detection in fault tolerant architectures. VTS D. A. Tran, Arnaud Virazel, Alberto Bosio, Luigi Dilillo, Patrick Girard, Aida Todri, Michael E. Imhof, Hans-Joachim Wunderlich
2012	Misc	`conf`	Advanced test methods for SRAMs. VTS Alberto Bosio, Luigi Dilillo, Patrick Girard, Serge Pravossoudovitch, Arnaud Virazel
2012	J	`jnl`	Analysis and Fault Modeling of Actual Resistive Defects in ATMEL TSTAC J. Electron. Test. Pierre-Didier Mauroux, Arnaud Virazel, Alberto Bosio, Luigi Dilillo, Patrick Girard, Serge Pravossoudovitch, Benoît Godard, Gilles Festes, Laurent Vachez
2012	B	`conf`	Coupling-based resistive-open defects in TAS-MRAM architectures. ETS Joao Azevedo, Arnaud Virazel, Alberto Bosio, Luigi Dilillo, Patrick Girard, Aida Todri, Guillaume Prenat, Jérémy Alvarez-Herault, Ken Mackay
2012	B	`conf`	Defect analysis in power mode control logic of low-power SRAMs. ETS Leonardo Bonet Zordan, Alberto Bosio, Luigi Dilillo, Patrick Girard, Aida Todri, Arnaud Virazel, Nabil Badereddine
2012	C	`conf`	Evaluation of test algorithms stress effect on SRAMs under neutron radiation. IOLTS Georgios Tsiligiannis, Luigi Dilillo, Alberto Bosio, Patrick Girard, Aida Todri, Arnaud Virazel, Antoine D. Touboul, Frederic Wrobel, Frédéric Saigné
2012	—	`conf`	Impact of Resistive-Bridge Defects in TAS-MRAM Architectures. Asian Test Symposium Joao Azevedo, Arnaud Virazel, Alberto Bosio, Luigi Dilillo, Patrick Girard, Aida Todri, Guillaume Prenat, Jérémy Alvarez-Herault, Ken Mackay
2012	J	`jnl`	Impact of Resistive-Bridging Defects in SRAM at Different Technology Nodes. J. Electron. Test. Renan Alves Fonseca, Luigi Dilillo, Alberto Bosio, Patrick Girard, Serge Pravossoudovitch, Arnaud Virazel, Nabil Badereddine
2012	A	`conf`	Impact of resistive-open defects on the heat current of TAS-MRAM architectures. DATE Joao Azevedo, Arnaud Virazel, Alberto Bosio, Luigi Dilillo, Patrick Girard, Aida Todri-Sanial, Guillaume Prenat, Jérémy Alvarez-Herault, Ken Mackay
2012	A	`conf`	Low-power SRAMs power mode control logic: Failure analysis and test solutions. ITC Leonardo Bonet Zordan, Alberto Bosio, Luigi Dilillo, Patrick Girard, Aida Todri, Arnaud Virazel, Nabil Badereddine
2012	—	`conf`	Peak Power Estimation: A Case Study on CPU Cores. Asian Test Symposium Paolo Bernardi, Mauricio de Carvalho, Ernesto Sánchez, Matteo Sonza Reorda, Alberto Bosio, Luigi Dilillo, Patrick Girard, Miroslav Valka
2012	—	`conf`	Power Supply Noise Sensor Based on Timing Uncertainty Measurements. Asian Test Symposium Miroslav Valka, Alberto Bosio, Luigi Dilillo, Patrick Girard, Aida Todri, Arnaud Virazel, P. Debaud, S. Guilhot
2012	B	`conf`	Through-Silicon-Via resistive-open defect analysis. ETS Carolina Metzler, Aida Todri, Alberto Bosio, Luigi Dilillo, Patrick Girard, Arnaud Virazel
2012	—	`conf`	Why and How Controlling Power Consumption during Test: A Survey. Asian Test Symposium Alberto Bosio, Luigi Dilillo, Patrick Girard, Aida Todri, Arnaud Virazel
2011	B	`conf`	A Functional Power Evaluation Flow for Defining Test Power Limits during At-Speed Delay Testing. ETS Miroslav Valka, Alberto Bosio, Luigi Dilillo, Patrick Girard, Serge Pravossoudovitch, Arnaud Virazel, Ernesto Sánchez, Mauricio de Carvalho, Matteo Sonza Reorda
2011	—	`conf`	A Hybrid Fault Tolerant Architecture for Robustness Improvement of Digital Circuits. Asian Test Symposium D. A. Tran, Arnaud Virazel, Alberto Bosio, Luigi Dilillo, Patrick Girard, Serge Pravossoudovitch, Hans-Joachim Wunderlich
2011	C	`conf`	A study of path delay variations in the presence of uncorrelated power and ground supply noise. DDECS Aida Todri, Alberto Bosio, Luigi Dilillo, Patrick Girard, Serge Pravossoudovitch, Arnaud Virazel
2011	—	`conf`	Effective Launch-to-Capture Power Reduction for LOS Scheme with Adjacent-Probability-Based X-Filling. Asian Test Symposium Kohei Miyase, Y. Uchinodan, Kazunari Enokimoto, Yuta Yamato, Xiaoqing Wen, Seiji Kajihara, Fangmei Wu, Luigi Dilillo, Alberto Bosio, Patrick Girard, Arnaud Virazel
2011	—	`conf`	Error Resilient Infrastructure for Data Transfer in a Distributed Neutron Detector. DFT Luigi Dilillo, Alberto Bosio, Miroslav Valka, Patrick Girard, Serge Pravossoudovitch, Arnaud Virazel
2011	—	`conf`	Failure Analysis and Test Solutions for Low-Power SRAMs. Asian Test Symposium Leonardo Bonet Zordan, Alberto Bosio, Luigi Dilillo, Patrick Girard, Serge Pravossoudovitch, Aida Todri, Arnaud Virazel, Nabil Badereddine
2011	—	`conf`	Neutron detection in atmospheric environment through static and dynamic SRAM-based test bench. LATW Luigi Dilillo, Paolo Rech, Jean-Marc Gallière, Patrick Girard, Frederic Wrobel, Frédéric Saigné
2011	C	`conf`	On using a SPICE-like TSTAC™ eFlash model for design and test. DDECS Pierre-Didier Mauroux, Arnaud Virazel, Alberto Bosio, Luigi Dilillo, Patrick Girard, Serge Pravossoudovitch, Benoît Godard, Gilles Festes, Laurent Vachez
2011	A	`conf`	On using address scrambling to implement defect tolerance in SRAMs. ITC Renan Alves Fonseca, Luigi Dilillo, Alberto Bosio, Patrick Girard, Serge Pravossoudovitch, Arnaud Virazel, Nabil Badereddine
2011	C	`conf`	Optimized march test flow for detecting memory faults in SRAM devices under bit line coupling. DDECS Leonardo Bonet Zordan, Alberto Bosio, Luigi Dilillo, Patrick Girard, Serge Pravossoudovitch, Arnaud Virazel, Nabil Badereddine
2011	—	`conf`	Power-Aware Test Pattern Generation for At-Speed LOS Testing. Asian Test Symposium Alberto Bosio, Luigi Dilillo, Patrick Girard, Aida Todri, Arnaud Virazel, Kohei Miyase, Xiaoqing Wen
2011	—	`conf`	Versatile march test generator for hands-on memory testing laboratory. MSE Jean-Marc Gallière, Luigi Dilillo
2010	J	`jnl`	A Comprehensive Analysis of Transition Fault Coverage and Test Power Dissipation for Launch-Off-Shift and Launch-Off-Capture Schemes. J. Low Power Electron. Fangmei Wu, Luigi Dilillo, Alberto Bosio, Patrick Girard, Serge Pravossoudovitch, Arnaud Virazel, Mohammad Tehranipoor, Xiaoqing Wen, Nisar Ahmed
2010	—	`conf`	A Comprehensive System-on-Chip Logic Diagnosis. Asian Test Symposium Youssef Benabboud, Alberto Bosio, Luigi Dilillo, Patrick Girard, Serge Pravossoudovitch, Arnaud Virazel, Olivia Riewer
2010	—	`conf`	A Memory Fault Simulator for Radiation-Induced Effects in SRAMs. Asian Test Symposium Paolo Rech, Alberto Bosio, Patrick Girard, Serge Pravossoudovitch, Arnaud Virazel, Luigi Dilillo
2010	A	`conf`	A roaming memory test bench for detecting particle induced SEUs. ITC Jean-Marc Gallière, Paolo Rech, Patrick Girard, Luigi Dilillo
2010	A*	`conf`	A statistical simulation method for reliability analysis of SRAM core-cells. DAC Renan Alves Fonseca, Luigi Dilillo, Alberto Bosio, Patrick Girard, Serge Pravossoudovitch, Arnaud Virazel, Nabil Badereddine
2010	B	`conf`	A two-layer SPICE model of the ATMEL TSTAC ETS Pierre-Didier Mauroux, Arnaud Virazel, Alberto Bosio, Luigi Dilillo, Patrick Girard, Serge Pravossoudovitch, Benoît Godard, Gilles Festes, Laurent Vachez
2010	C	`conf`	Analysis of power consumption and transition fault coverage for LOS and LOC testing schemes. DDECS Fangmei Wu, Luigi Dilillo, Alberto Bosio, Patrick Girard, Serge Pravossoudovitch, Arnaud Virazel, Junxia Ma, Wei Zhao, Mohammad Tehranipoor, Xiaoqing Wen
2010	B	`conf`	Analysis of resistive-bridging defects in SRAM core-cells: A comparative study from 90nm down to 40nm technology nodes. ETS Renan Alves Fonseca, Luigi Dilillo, Alberto Bosio, Patrick Girard, Serge Pravossoudovitch, Arnaud Virazel, Nabil Badereddine
2010	C	`conf`	Analysis of root causes of alpha sensitivity variations on microprocessors manufactured using different cell layouts. IOLTS Paolo Rech, Michelangelo Grosso, Fabio Melchiori, Domenico Loparco, Davide Appello, Luigi Dilillo, Alessandro Paccagnella, Matteo Sonza Reorda
2010	Misc	`conf`	Detecting NBTI induced failures in SRAM core-cells. VTS Renan Alves Fonseca, Luigi Dilillo, Alberto Bosio, Patrick Girard, Serge Pravossoudovitch, Arnaud Virazel, Nabil Badereddine
2010	—	`conf`	Impact of Resistive-Bridging Defects in SRAM Core-Cell. DELTA Renan Alves Fonseca, Luigi Dilillo, Alberto Bosio, Patrick Girard, Serge Pravossoudovitch, Arnaud Virazel, Nabil Badereddine
2010	A	`conf`	Is test power reduction through X-filling good enough? ITC Fangmei Wu, Luigi Dilillo, Alberto Bosio, Patrick Girard, Serge Pravossoudovitch, Arnaud Virazel, Mohammad Tehranipoor, Kohei Miyase, Xiaoqing Wen, Nisar Ahmed
2010	A	`conf`	Parity prediction synthesis for nano-electronic gate designs. ITC D. A. Tran, Arnaud Virazel, Alberto Bosio, Luigi Dilillo, Patrick Girard, Serge Pravossoudovitch, Hans-Joachim Wunderlich
2010	B	`conf`	Setting test conditions for improving SRAM reliability. ETS Renan Alves Fonseca, Luigi Dilillo, Alberto Bosio, Patrick Girard, Serge Pravossoudovitch, Arnaud Virazel, Nabil Badereddine
2009	A	`conf`	A new design-for-test technique for SRAM core-cell stability faults. DATE Alexandre Ney, Luigi Dilillo, Patrick Girard, Serge Pravossoudovitch, Arnaud Virazel, Magali Bastian, Vincent Gouin
2009	C	`conf`	Comprehensive bridging fault diagnosis based on the SLAT paradigm. DDECS Youssef Benabboud, Alberto Bosio, Luigi Dilillo, Patrick Girard, Serge Pravossoudovitch, Arnaud Virazel, Laroussi Bouzaida, Isabelle Izaute
2009	—	`conf`	Delay Fault Diagnosis in Sequential Circuits. Asian Test Symposium Youssef Benabboud, Alberto Bosio, Luigi Dilillo, Patrick Girard, Serge Pravossoudovitch, Arnaud Virazel, Olivia Riewer
2009	A	`conf`	NAND flash testing: A preliminary study on actual defects. ITC Pierre-Didier Mauroux, Arnaud Virazel, Alberto Bosio, Luigi Dilillo, Patrick Girard, Serge Pravossoudovitch, Benoît Godard
2008	A	`conf`	A History-Based Diagnosis Technique for Static and Dynamic Faults in SRAMs. ITC Alexandre Ney, Alberto Bosio, Luigi Dilillo, Patrick Girard, Serge Pravossoudovitch, Arnaud Virazel, Magali Bastian
2007	J	`jnl`	Analysis and Test of Resistive-Open Defects in SRAM Pre-Charge Circuits. J. Electron. Test. Luigi Dilillo, Patrick Girard, Serge Pravossoudovitch, Arnaud Virazel, Magali Bastian
2007	C	`conf`	March CRF: an Efficient Test for Complex Read Faults in SRAM Memories. DDECS Luigi Dilillo, Bashir M. Al-Hashimi
2006	J	`jnl`	ADOFs and Resistive-ADOFs in SRAM Address Decoders: Test Conditions and March Solutions. J. Electron. Test. Luigi Dilillo, Patrick Girard, Serge Pravossoudovitch, Arnaud Virazel, Simone Borri, Magali Bastian Hage-Hassan
2006	C	`conf`	March Pre: an Efficient Test for Resistive-Open Defects in the SRAM Pre-charge Circuit. DDECS Luigi Dilillo, Patrick Girard, Serge Pravossoudovitch, Arnaud Virazel, Magali Bastian
2006	A	`conf`	Minimizing test power in SRAM through reduction of pre-charge activity. DATE Luigi Dilillo, Paul M. Rosinger, Bashir M. Al-Hashimi, Patrick Girard
2006	J	`jnl`	Reducing Power Dissipation in SRAM during Test. J. Low Power Electron. Luigi Dilillo, Paul M. Rosinger, Bashir M. Al-Hashimi, Patrick Girard
2005	J	`jnl`	Analysis of Dynamic Faults in Embedded-SRAMs: Implications for Memory Test. J. Electron. Test. Simone Borri, Magali Hage-Hassan, Luigi Dilillo, Patrick Girard, Serge Pravossoudovitch, Arnaud Virazel
2005	Misc	`conf`	Data Retention Fault in SRAM Memories: Analysis and Detection Procedures. VTS Luigi Dilillo, Patrick Girard, Serge Pravossoudovitch, Arnaud Virazel, Magali Bastian Hage-Hassan
2005	J	`jnl`	Efficient March Test Procedure for Dynamic Read Destructive Fault Detection in SRAM Memories. J. Electron. Test. Luigi Dilillo, Patrick Girard, Serge Pravossoudovitch, Arnaud Virazel, Simone Borri, Magali Hage-Hassan
2005	B	`conf`	Resistive-open defect influence in SRAM pre-charge circuits: analysis and characterization. ETS Luigi Dilillo, Patrick Girard, Serge Pravossoudovitch, Arnaud Virazel, Magali Bastian Hage-Hassan
2005	A*	`conf`	Resistive-open defect injection in SRAM core-cell: analysis and comparison between 0.13 µm and 90 nm technologies. DAC Luigi Dilillo, Patrick Girard, Serge Pravossoudovitch, Arnaud Virazel, Magali Bastian
2004	B	`conf`	Dynamic read destructive fault in embedded-SRAMs: analysis and march test solution. ETS Luigi Dilillo, Patrick Girard, Serge Pravossoudovitch, Arnaud Virazel, Simone Borri, Magali Bastian Hage-Hassan
2004	Misc	`conf`	March iC-: An Improved Version of March C- for ADOFs Detection. VTS Luigi Dilillo, Patrick Girard, Serge Pravossoudovitch, Arnaud Virazel, Simone Borri
2004	—	`conf`	Resistive-Open Defects in Embedded-SRAM Core Cells: Analysis and March Test Solution. Asian Test Symposium Luigi Dilillo, Patrick Girard, Serge Pravossoudovitch, Arnaud Virazel, Simone Borri, Magali Bastian Hage-Hassan
2003	—	`conf`	Comparison of Open and Resistive-Open Defect Test Conditions in SRAM Address Decoders. Asian Test Symposium Luigi Dilillo, Patrick Girard, Serge Pravossoudovitch, Arnaud Virazel, Simone Borri