Ludo Weyten

40 papers C 6Journal 24Unranked 10
YearRankTypeTitle / Venue / Authors
2013 J jnl
A Describing Function Study of Saturated Quantization and Its Application to the Stability Analysis of Multi-Bit Sigma Delta Modulators.
IEEE Trans. Circuits Syst. I Regul. Pap.
Pieter Rombouts, Maarten De Bock, Jeroen De Maeyer, Ludo Weyten
2013 J jnl
Calibration of DAC Mismatch Errors in ΣΔ ADCs Based on a Sine-Wave Measurement.
IEEE Trans. Circuits Syst. II Express Briefs
Maarten De Bock, Xinpeng Xing, Ludo Weyten, Georges G. E. Gielen, Pieter Rombouts
2011 J jnl
Validation of Symbolic Expressions in Circuit Analysis E-Learning.
IEEE Trans. Educ.
Ludo Weyten, Pieter Rombouts, Benoit Catteau, Maarten De Bock
2010 C conf
A 14-bit 250MS/s digital to analog converter with binary weighted Redundant Signed Digit coding.
ISCAS
Benoit Catteau, Bart De Vuyst, Pieter Rombouts, Ludo Weyten
2010 J jnl
Comments on "Performance Analysis of a Hybrid Incremental and Cyclic A/D Conversion Principle".
IEEE Trans. Circuits Syst. I Regul. Pap.
Pieter Rombouts, Jeroen De Maeyer, Ludo Weyten
2009 J jnl
Nyquist-criterion based design of a CT SigmaDelta-ADC with a reduced number of comparators.
Integr.
Jeroen De Maeyer, Pieter Rombouts, Ludo Weyten
2009 J jnl
Web-Based Trainer for Electrical Circuit Analysis.
IEEE Trans. Educ.
Ludo Weyten, Pieter Rombouts, Jeroen De Maeyer
2008 J jnl
An On-Line Calibration Technique for Mismatch Errors in High-Speed DACs.
IEEE Trans. Circuits Syst. I Regul. Pap.
Benoit Catteau, Pieter Rombouts, Johan Raman, Ludo Weyten
2008 J jnl
An Unconstrained Architecture for Systematic Design of Higher Order SigmaDelta Force-Feedback Loops.
IEEE Trans. Circuits Syst. I Regul. Pap.
Johan Raman, Pieter Rombouts, Ludo Weyten
2008 — conf
Redundant signed digit coding in binary weighted DACs.
ICECS
Benoit Catteau, Pieter Rombouts, Ludo Weyten
2007 C conf
A Digital Calibration Technique for the Correction of Glitches in High-Speed DAC's.
ISCAS
Benoit Catteau, Pieter Rombouts, Ludo Weyten
2007 J jnl
A delay-based complex double-sampled resonator for use in ƒ
IEICE Electron. Express
Stijn Reekmans, Pieter Rombouts, Ludo Weyten
2007 C conf
An Unconstrained Architecture for High-Order Sigma Delta Force-Feedback Inertial Sensors.
ISCAS
Johan Raman, Pieter Rombouts, Ludo Weyten
2007 J jnl
Efficient Multibit Quantization in Continuous-Time Sigma Delta Modulators.
IEEE Trans. Circuits Syst. I Regul. Pap.
Jeroen De Maeyer, Pieter Rombouts, Ludo Weyten
2007 J jnl
Mismatch Insensitive Double-Sampling Quadrature Bandpass SigmaDelta Modulation.
IEEE Trans. Circuits Syst. I Regul. Pap.
Stijn Reekmans, Pieter Rombouts, Ludo Weyten
2007 C conf
Quadrature Mismatch Shaping Techniques for Fully Differential Circuits.
ISCAS
Stijn Reekmans, Pieter Rombouts, Ludo Weyten
2006 C conf
Nyquist criterion based design of continuous time Sigma Delta modulators.
ISCAS
Jeroen De Maeyer, Pieter Rombouts, Ludo Weyten
2006 — conf
Nyquist-criterion based design of a CT ΣΔ-ADC with a reduced number of comparators.
ICECS
Jeroen De Maeyer, Pieter Rombouts, Ludo Weyten
2006 J jnl
Quadrature Mismatch Shaping for Digital-to-Analog Converters.
IEEE Trans. Circuits Syst. I Regul. Pap.
Stijn Reekmans, Jeroen De Maeyer, Pieter Rombouts, Ludo Weyten
2006 — conf
Quadrature Mismatch Shaping with a Complex, Data Directed Swapper.
ICECS
Stijn Reekmans, Benoit Catteau, Pieter Rombouts, Ludo Weyten
2006 C conf
Quadrature mismatch shaping with a complex, tree structured DAC.
ISCAS
Stijn Reekmans, Jeroen De Maeyer, Pieter Rombouts, Ludo Weyten
2005 J jnl
A versatile Nyquist-rate A/D converter with 16-18 bit performance for sensor readout applications.
Integr.
Pieter Rombouts, Ludo Weyten
2005 J jnl
Design of double-sampling ΣΔ modulation A/D converters with bilinear integrators.
IEEE Trans. Circuits Syst. I Regul. Pap.
Pieter Rombouts, Jeroen De Maeyer, Ludo Weyten
2005 — conf
STF behaviour in a CT ΔΣ modulator.
ICECS
Jeroen De Maeyer, Johan Raman, Pieter Rombouts, Ludo Weyten
2004 J jnl
A double-sampling extended-counting ADC.
IEEE J. Solid State Circuits
Jeroen De Maeyer, Pieter Rombouts, Ludo Weyten
2004 — conf
Addressing static and dynamic errors in bandpass unit element multibit DAC's.
ISCAS (1)
Jeroen De Maeyer, Pieter Rombouts, Ludo Weyten
2004 — conf
Systematic design of double-sampling Sigma Delta ADC's with modified NTF.
ISCAS (1)
Pieter Rombouts, Jeroen De Maeyer, Johan Raman, Ludo Weyten
2004 J jnl
Systematic design of double-sampling ΣΔ A/D converters with a modified noise transfer function.
IEEE Trans. Circuits Syst. II Express Briefs
Pieter Rombouts, Ludo Weyten
2003 J jnl
A 250-kHz 94-dB double-sampling ΣΔ modulation A/D converter with a modified noise transfer function.
IEEE J. Solid State Circuits
Pieter Rombouts, Jeroen De Maeyer, Ludo Weyten
2003 J jnl
An approach to tackle quantization noise folding in double-sampling ΣΔ modulation A/D converters.
IEEE Trans. Circuits Syst. II Express Briefs
Pieter Rombouts, Johan Raman, Ludo Weyten
2002 — conf
An efficient technique to eliminate quantisation noise folding in double-sampling Sigma-Delta modulators.
ISCAS (3)
Pieter Rombouts, Johan Raman, Ludo Weyten
2001 J jnl
A 13.5-b 1.2-V micropower extended counting A/D converter.
IEEE J. Solid State Circuits
Pieter Rombouts, Wim De Wilde, Ludo Weyten
2001 J jnl
Composite functions in an orthogonal polynomial base.
Signal Process.
Johan Raman, Ludo Weyten
2000 J jnl
Time domain adaptive delay estimation.
IEEE Trans. Signal Process.
Johan Raman, Ludo Weyten
1999 — conf
Adaptive fractional delay estimation without lock-up.
ICECS
Johan Raman, Ludo Weyten
1999 — conf
On noise suppression in adaptive delay estimation.
ISSPA
Johan Raman, Ludo Weyten
1998 — conf
Dynamic element matching for pipelined A/D conversion.
ICECS
Pieter Rombouts, Ludo Weyten
1990 J jnl
Multiple storage adaptive multi-trees.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Wim De Pauw, Ludo Weyten
1989 J jnl
Performance prediction for adaptive quad tree graphical data structures.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Ludo Weyten, Wim De Pauw
1989 J jnl
Quad list quad trees: a geometrical data structure with improved performance for large region queries.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Ludo Weyten, Wim De Pauw