Luca Sterpone

202 papers A 15B 16C 44Misc 1Journal 45Unranked 77
YearRankTypeTitle / Venue / Authors
2026 J jnl
A novel FPGA-based time-to-digital converter featuring machine learning-aided self-calibration.
Intell. Syst. Appl.
Arash Amini Bardpareh, Eleonora Vacca, Davide Nicolini, Corrado De Sio, Sarah Azimi, Luca Sterpone, Elisa Fiorina, Emanuele Maria Data, Felix Mas Milian
2025 — conf
An Integrated Flow for Predicting Radiation Effects in CubeSat Onboard Electronics.
ICECS
Eleonora Vacca, Corrado De Sio, Luca Sterpone
2025 — conf
Cutting-Edge Strategies for Radiation Effect Estimation on Asteroids Space Mission: Invited Paper.
CF (Companion)
Eleonora Vacca, Sarah Azimi, Luca Sterpone
2025 C conf
Enabling Time-Aware Priority Traffic Management over Distributed FPGA Nodes.
DSD
Alberto Scionti, Paolo Savio, Francesco Lubrano, Federico Stirano, Antonino Nespola, Olivier Terzo, Corrado De Sio, Luca Sterpone
2025 J jnl
Enabling Time-Aware Priority Traffic Management over Distributed FPGA Nodes.
CoRR
Alberto Scionti, Paolo Savio, Francesco Lubrano, Federico Stirano, Antonino Nespola, Olivier Terzo, Corrado De Sio, Luca Sterpone
2025 — conf
Fault Tolerant Multi-object Tracking via Temporal Consistency Filtering.
ICIAP (2)
Rosario Milazzo, Sophie M. Fosson, Lia Morra, Luca Sterpone
2025 J jnl
From detection to intervention: An end-to-end system for recognizing the "signal for help" gesture in real-time.
Intell. Syst. Appl.
Federico Buccellato, Eleonora Vacca, Sarah Azimi, Corrado De Sio, Luca Sterpone
2025 — conf
High-Precision Time Measurement on FPGA: An Optimized TDC Approach.
ICECS
Arash Amini Bardpareh, Eleonora Vacca, Corrado De Sio, Sarah Azimi, Luca Sterpone, Elisa Fiorina, Emanuele Maria Data, Felix Mas Milian
2025 — conf
Mitigating Cross-Domain SEU Corruption in FPGA-Based AI Accelerators for Space Applications: Invited Paper.
CF (Companion)
Sarah Azimi, Eleonora Vacca, Corrado De Sio, Luca Sterpone, Andrea Portaluri
2025 C conf
On-Hardware Resilience Analysis of DPUAccelerated CNNs on FPGA-Based Systems.
DSD
Federico Buccellato, Corrado De Sio, Sarah Azimi, Luca Sterpone
2025 — conf
POSTER: AI-Powered Anomaly Detection for Satellite Telemetry.
CF
Federico Buccellato, Davide Nicolini, Eleonora Vacca, Corrado De Sio, Luca Sterpone
2025 — conf
RePAIR: Reconfigurable Platform for AI Resilience Within RISC-V Ecosystem.
ARC
Giorgio Cora, Eleonora Vacca, Corrado De Sio, Sarah Azimi, Luca Sterpone
2025 B conf
Routino: Accelerating FPGA Routing Through Efficient Memory Representation.
FPL
Davide Nicolini, Corrado De Sio, Eleonora Vacca, Luca Sterpone
2025 J jnl
Self-Supervised Pretraining and Quantization for Fault Tolerant Neural Networks: Friend or Foe?
IEEE Access
Rosario Milazzo, Sophie M. Fosson, Lia Morra, Luca Sterpone
2024 C conf
A New Reliability Analysis of RISC-V Soft Processor for Safety-Critical Systems.
DDECS
Giorgio Cora, Corrado De Sio, Daniele Rizzieri, Sarah Azimi, Luca Sterpone
2024 — conf
A Novel Robust Core for Detecting Node Failures in FPGA Clusters.
CF
Giorgio Cora, Corrado De Sio, Sarah Azimi, Luca Sterpone
2024 — conf
Assessment of RISC-V Processor Suitability for Satellite Applications.
CF (Companion)
Eleonora Vacca, Giorgio Cora, Sarah Azimi, Luca Sterpone
2024 J jnl
CNN-Oriented Placement Algorithm for High-Performance Accelerators on Rad-Hard FPGAs.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Luca Sterpone, Sarah Azimi, Corrado De Sio
2024 — conf
Exploring the Resiliency of Hardware CNN for Aerospace Application.
SMACD
Corrado De Sio, Giorgio Cora, Sarah Azimi, Eleonora Vacca, Luca Sterpone
2024 C conf
On the Fault Tolerance of Self-Supervised Training in Convolutional Neural Networks.
DDECS
Rosario Milazzo, Vincenzo De Marco, Corrado De Sio, Sophie M. Fosson, Lia Morra, Luca Sterpone
2024 — conf
Scalable K-Nearest Neighbors Implementation using Distributed Embedded Systems.
CF
Corrado De Sio, Andrea Avignone, Luca Sterpone, Silvia Chiusano
2024 A conf
Toward Fault-Tolerant Applications on Reconfigurable Systems-on-Chip.
ITC
Corrado De Sio, Luca Sterpone
2024 — conf
ZOR: Zero Overhead Reliability Strategies for AI Accelerators.
NewCAS
Eleonora Vacca, Sarah Azimi, Luca Sterpone
2023 C conf
A Comprehensive Analysis of Transient Errors on Systolic Arrays.
DDECS
Eleonora Vacca, Sarah Azimi, Luca Sterpone
2023 — conf
A Framework for Uniformly Analyze and Mitigate Radiation-effects on FPGAs for Aerospace.
CF
Luca Sterpone, Sarah Azimi, Corrado De Sio
2023 A conf
Assessing Convolutional Neural Networks Reliability through Statistical Fault Injections.
DATE
Annachiara Ruospo, Gabriele Gavarini, Corrado De Sio, Juan-David Guerrero-Balaguera, Luca Sterpone, Matteo Sonza Reorda, Ernesto Sánchez, Riccardo Mariani, Joseph Aribido, Jyotika Athavale
2023 — conf
Assessing the Robustness of Real-Time Operating System on Soft Processor against Multiple Bit Upset.
CF
Andrea Portaluri, Corrado De Sio, Luca Sterpone
2023 C conf
Design Techniques for Multi-Core Neural Network Accelerators on Radiation-Hardened FPGAs.
ISPDC
Andrea Portaluri, Sarah Azimi, Luca Sterpone
2023 C conf
Enhanced Video Surveillance Systems for "Signal for Help" Detection on Edge Devices.
ISTAS
Sarah Azimi, Corrado De Sio, Luca Sterpone
2023 A conf
EuFRATE: European FPGA Radiation-hardened Architecture for Telecommunications.
DATE
Ludovica Bozzoli, Antonino Catanese, Emilio Fazzoletto, Eugenio Scarpa, Diana Goehringer, Sergio A. Pertuz, Lester Kalms, Cornelia Wulf, Najdet Charaf, Luca Sterpone, Sarah Azimi, Daniele Rizzieri, Salvatore Gabriele La Greca, David Merodio Codinachs, Stephen King
2023 J jnl
Fighting for a future free from violence: A framework for real-time detection of "Signal for Help".
Intell. Syst. Appl.
Sarah Azimi, Corrado De Sio, Francesco Carlucci, Luca Sterpone
2023 — conf
High-Performance SET Hardening Technique for Vision-Oriented Applications.
SMACD
Corrado De Sio, Luca Sterpone
2023 — conf
Programmable SEL Test Monitoring System for Radiation Hardness Assurance.
DSN-S
Daniele Rizzieri, Sarah Azimi, Luca Sterpone, Corrado De Sio, Thomas Borel, Viyas Gupta, Margherita Cardi
2023 — conf
PyXEL: Exploring Bitstream Analysis to Assess and Enhance the Robustness of Designs on FPGAs.
SMACD
Corrado De Sio, Sarah Azimi, Luca Sterpone, David Merodio Codinachs, Filomena Decuzzi
2023 — conf
Reliability Analysis of Microarchitectural Faults in GPGPU-based HPC Systems.
CF
Corrado De Sio, Luca Sterpone, Sarah Azimi
2023 C conf
RunSAFER: A Novel Runtime Fault Detection Approach for Systolic Array Accelerators.
ICCD
Eleonora Vacca, Giorgio Ajmone, Luca Sterpone
2022 — conf
A Placement-Oriented Mitigation Technique for Single Event Effect in Monolithic 3D IC.
SMACD
Sarah Azimi, Corrado De Sio, Luca Sterpone
2022 J jnl
An Automated Continuous Integration Multitest Platform for Automotive Systems.
IEEE Syst. J.
Boyang Du, Sarah Azimi, Annarita Moramarco, Davide Sabena, Filippo Parisi, Luca Sterpone
2022 C conf
Analysis and Mitigation of Soft-Errors on High Performance Embedded GPUs.
ISPDC
Luca Sterpone, Sarah Azimi, Corrado De Sio, Filippo Parisi
2022 — conf
Analysis of Proton-induced Single Event Effect in the On-Chip Memory of Embedded Process.
DFT
Corrado De Sio, Sarah Azimi, Luca Sterpone, David Merodio Codinachs
2022 — ed.
CF '22: 19th ACM International Conference on Computing Frontiers, Turin, Italy, May 17 - 22, 2022
CF
Luca Sterpone, Andrea Bartolini, Anastasiia Butko
2022 J jnl
Evaluating low-level software-based hardening techniques for configurable GPU architectures.
J. Supercomput.
Marcio M. Gonçalves, Josie E. Rodriguez Condia, Matteo Sonza Reorda, Luca Sterpone, José Rodrigo Azambuja
2022 J jnl
FireNN: Neural Networks Reliability Evaluation on Hybrid Platforms.
IEEE Trans. Emerg. Top. Comput.
Corrado De Sio, Sarah Azimi, Luca Sterpone
2022 — conf
On the Reliability of Real-Time Operating System on Embedded Soft Processor for Space Applications.
ARCS
Andrea Portaluri, Sarah Azimi, Corrado De Sio, Daniele Rizzieri, Luca Sterpone
2022 C conf
Radiation-induced Effects on DMA Data Transfer in Reconfigurable Devices.
IOLTS
Andrea Portaluri, Sarah Azimi, Corrado De Sio, Luca Sterpone, David Merodio Codinachs
2022 B conf
Test, Reliability and Functional Safety Trends for Automotive System-on-Chip.
ETS
Francesco Angione, Davide Appello, Joseph Aribido, Jyotika Athavale, Nicolò Bellarmino, Paolo Bernardi, Riccardo Cantoro, Corrado De Sio, Tommaso Foscale, Gabriele Gavarini, Juan-David Guerrero-Balaguera, Martin Huch, Giusy Iaria, Tobias Kilian, Riccardo Mariani, Raffaele Martone, Annachiara Ruospo, Ernesto Sánchez, Ulf Schlichtmann, Giovanni Squillero, Matteo Sonza Reorda, Luca Sterpone, Vincenzo Tancorre, Roberto Ugioli
2021 A conf
A 3-D LUT Design for Transient Error Detection Via Inter-Tier In-Silicon Radiation Sensor.
DATE
Sarah Azimi, Corrado De Sio, Luca Sterpone
2021 — conf
A Neutron Generator Testing Platform for the Radiation Analysis of SRAM-based FPGAs.
I2MTC
Ludovica Bozzoli, Corrado De Sio, Boyang Du, Luca Sterpone
2021 C conf
A New Domains-based Isolation Design Flow for Reconfigurable SoCs.
IOLTS
Andrea Portaluri, Corrado De Sio, Sarah Azimi, Luca Sterpone
2021 J jnl
A Radiation-Hardened CMOS Full-Adder Based on Layout Selective Transistor Duplication.
IEEE Trans. Very Large Scale Integr. Syst.
Sarah Azimi, Corrado De Sio, Luca Sterpone
2021 J jnl
DYRE: a DYnamic REconfigurable solution to increase GPGPU's reliability.
J. Supercomput.
Josie E. Rodriguez Condia, Pierpaolo Narducci, Matteo Sonza Reorda, Luca Sterpone
2021 — conf
Design and Mitigation Techniques of Radiation Induced SEEs on Open-Source Embedded Static RAMs.
VLSI-SoC (Selected Papers)
Sarah Azimi, Corrado De Sio, Andrea Portaluri, Luca Sterpone
2021 C conf
On the Evaluation of SEEs on Open-Source Embedded Static RAMs.
VLSI-SoC
Sarah Azimi, Corrado De Sio, Luca Sterpone
2021 — conf
SEU Evaluation of Hardened-by-Replication Software in RISC- V Soft Processor.
DFT
Corrado De Sio, Sarah Azimi, Andrea Portaluri, Luca Sterpone
2020 — conf
A New Single Event Transient Hardened Floating Gate Configurable Logic Circuit.
NEWCAS
Sarah Azimi, Corrado De Sio, Weitao Yang, Luca Sterpone
2020 C conf
A dynamic hardware redundancy mechanism for the in-field fault detection in cores of GPGPUs.
DDECS
Josie E. Rodriguez Condia, Pierpaolo Narducci, Matteo Sonza Reorda, Luca Sterpone
2020 Misc conf
A dynamic reconfiguration mechanism to increase the reliability of GPGPUs.
VTS
Josie E. Rodriguez Condia, Pierpaolo Narducci, Matteo Sonza Reorda, Luca Sterpone
2020 — conf
An Emulation Platform for Evaluating the Reliability of Deep Neural Networks.
DFT
Corrado De Sio, Sarah Azimi, Luca Sterpone
2020 J jnl
An Optimized Frame-Driven Routing Algorithm for Reconfigurable SRAM-Based FPGAs.
IEEE Access
Ludovica Bozzoli, Luca Sterpone
2020 — conf
Analyzing the Sensitivity of GPU Pipeline Registers to Single Events Upsets.
ISVLSI
Josie E. Rodriguez Condia, Marcio Gonçalves, José Rodrigo Azambuja, Matteo Sonza Reorda, Luca Sterpone
2020 A conf
Digital Design Techniques for Dependable High Performance Computing.
ITC
Sarah Azimi, Luca Sterpone
2020 — conf
Evaluating Software-based Hardening Techniques for General-Purpose Registers on a GPGPU.
LATS
Marcio Gonçalves, José Rodrigo Azambuja, Josie E. Rodriguez Condia, Matteo Sonza Reorda, Luca Sterpone
2020 J jnl
Functional Failure Rate Due to Single-Event Transients in Clock Distribution Networks.
CoRR
Thomas Lange, Maximilien Glorieux, Dan Alexandrescu, Luca Sterpone
2020 C conf
In-Circuit Mitigation Approach of Single Event Transients for 45nm Flip-Flops.
IOLTS
Sarah Azimi, Corrado De Sio, Luca Sterpone
2020 C conf
Machine Learning Clustering Techniques for Selective Mitigation of Critical Design Features.
IOLTS
Thomas Lange, Aneesh Balakrishnan, Maximilien Glorieux, Dan Alexandrescu, Luca Sterpone
2020 J jnl
Machine Learning Clustering Techniques for Selective Mitigation of Critical Design Features.
CoRR
Thomas Lange, Aneesh Balakrishnan, Maximilien Glorieux, Dan Alexandrescu, Luca Sterpone
2020 J jnl
Machine Learning to Tackle the Challenges of Transient and Soft Errors in Complex Circuits.
CoRR
Thomas Lange, Aneesh Balakrishnan, Maximilien Glorieux, Dan Alexandrescu, Luca Sterpone
2020 J jnl
On the Estimation of Complex Circuits Functional Failure Rate by Machine Learning Techniques.
CoRR
Thomas Lange, Aneesh Balakrishnan, Maximilien Glorieux, Dan Alexandrescu, Luca Sterpone
2020 — conf
On the Evaluation of SEU Effects on AXI Interconnect Within AP-SoCs.
ARCS
Corrado De Sio, Sarah Azimi, Luca Sterpone
2020 A conf
RESCUE: Interdependent Challenges of Reliability, Security and Quality in Nanoelectronic Systems.
DATE
Maksim Jenihhin, Said Hamdioui, Matteo Sonza Reorda, Milos Krstic, Peter Langendörfer, Christian Sauer, Anton Klotz, Michael Hübner, Jörg Nolte, Heinrich Theodor Vierhaus, Georgios N. Selimis, Dan Alexandrescu, Mottaqiallah Taouil, Geert Jan Schrijen, Jaan Raik, Luca Sterpone, Giovanni Squillero, Zoya Dyka
2020 — conf
Soft-Error Analysis of Self-reconfiguration Controllers for Safety Critical Dynamically Reconfigurable FPGAs.
ARC
Ludovica Bozzoli, Luca Sterpone
2019 J jnl
A new CAD tool for Single Event Transient Analysis and mitigation on Flash-based FPGAs.
Integr.
Sarah Azimi, Boyang Du, Luca Sterpone, David Merodio Codinachs, Raoul Grimoldi, L. Cattaneo
2019 C conf
A new FPGA-based Detection Method for Spurious Variations in PCBA Power Distribution Network.
DDECS
Sergei Odintsov, Ludovica Bozzoli, Corrado De Sio, Luca Sterpone, Artur Jutman
2019 — conf
A new Method for the Analysis of Radiation-induced Effects in 3D VLSI Face-to-Back LUTs.
SMACD
Luca Sterpone, Ludovica Bozzoli, Corrado De Sio, Boyang Du, Sarah Azimi
2019 J jnl
Analyzing Radiation-Induced Transient Errors on SRAM-Based FPGAs by Propagation of Broadening Effect.
IEEE Access
Corrado De Sio, Sarah Azimi, Luca Sterpone, Boyang Du
2019 — conf
Functional Failure Rate Due to Single-Event Transients in Clock Distribution Networks.
DTIS
Thomas Lange, Maximilien Glorieux, Dan Alexandrescu, Luca Sterpone
2019 C conf
Machine Learning to Tackle the Challenges of Transient and Soft Errors in Complex Circuits.
IOLTS
Thomas Lange, Aneesh Balakrishnan, Maximilien Glorieux, Dan Alexandrescu, Luca Sterpone
2019 — conf
On the Estimation of Complex Circuits Functional Failure Rate by Machine Learning Techniques.
DSN (Supplements)
Thomas Lange, Aneesh Balakrishnan, Maximilien Glorieux, Dan Alexandrescu, Luca Sterpone
2019 B conf
On the Evaluation of the PIPB Effect within SRAM-based FPGAs.
ETS
Corrado De Sio, Sarah Azimi, Luca Sterpone
2019 — conf
On the Reliability of Convolutional Neural Network Implementation on SRAM-based FPGA.
DFT
Boyang Du, Sarah Azimi, Corrado De Sio, Ludovica Bozzoli, Luca Sterpone
2019 — conf
On the evaluation of SEU effects in GPGPUs.
LATS
Boyang Du, Josie E. Rodriguez Condia, Matteo Sonza Reorda, Luca Sterpone
2019 J jnl
RESCUE: Interdependent Challenges of Reliability, Security and Quality in Nanoelectronic Systems.
CoRR
Maksim Jenihhin, Said Hamdioui, Matteo Sonza Reorda, Milos Krstic, Peter Langendörfer, Christian Sauer, Anton Klotz, Michael Hübner, Jörg Nolte, Heinrich Theodor Vierhaus, Georgios N. Selimis, Dan Alexandrescu, Mottaqiallah Taouil, Geert Jan Schrijen, Jaan Raik, Luca Sterpone, Giovanni Squillero, Zoya Dyka
2019 — conf
ReM: A Reconfigurable Multipotent Cell for New Distributed Reconfigurable Architectures.
ARC
Ludovica Bozzoli, Luca Sterpone
2018 — conf
A Novel Error Rate Estimation Approach forUltraScale+ SRAM-based FPGAs.
AHS
Luca Sterpone, Sarah Azimi, Ludovica Bozzoli, Boyang Du, Thomas Lange, Maximilien Glorieux, Dan Alexandrescu, Cesar Boatella Polo, David Merodio Codinachs
2018 C conf
About the functional test of the GPGPU scheduler.
IOLTS
Boyang Du, Josie E. Rodriguez Condia, Matteo Sonza Reorda, Luca Sterpone
2018 — conf
Fast Partial Reconfiguration on SRAM-Based FPGAs: A Frame-Driven Routing Approach.
ARC
Luca Sterpone, Ludovica Bozzoli
2018 C conf
IbIS: Interface-based Interconnection Structure for Dynamically Reconfigurable FPGAs.
ISCAS
Ludovica Bozzoli, Luca Sterpone
2018 — conf
MATS**: An On-Line Testing Approach for Reconfigurable Embedded Memories.
DFT
Ludovica Bozzoli, Luca Sterpone
2018 J jnl
OLT(RE)
IEEE Trans. Emerg. Top. Comput.
Dario Cozzi, Sebastian Korf, Luca Cassano, Jens Hagemeyer, Andrea Domenici, Cinzia Bernardeschi, Luca Sterpone, Mario Porrmann
2018 J jnl
On the analysis of radiation-induced Single Event Transients on SRAM-based FPGAs.
Microelectron. Reliab.
Sarah Azimi, Luca Sterpone, Boyang Du, Luca Boragno
2018 B conf
On the mitigation of single event transients on flash-based FPGAs.
ETS
Sarah Azimi, Boyang Du, Luca Sterpone
2018 C conf
PyXEL: An Integrated Environment for the Analysis of Fault Effects in SRAM-Based FPGA Routing.
RSP
Ludovica Bozzoli, Corrado De Sio, Luca Sterpone, Cinzia Bernardeschi
2018 — conf
SETA: A CAD Tool for Single Event Transient Analysis and Mitigation on Flash-Based FPGAs.
SMACD
Sarah Azimi, Boyang Du, Luca Sterpone, David Merodio Codinachs, L. Cattaneo
2017 J jnl
A new approach for Total Ionizing Dose effect analysis on Flash-based FPGA.
Microelectron. Reliab.
Qiutao Zhang, Sarah Azimi, Germano La Vaccara, Luca Sterpone, Boyang Du
2017 J jnl
A novel tool-flow for zero-overhead cross-domain error resilient partially reconfigurable X-TMR for SRAM-based FPGAs.
J. Syst. Archit.
Luis Andrés Cardona, Anees Ullah, Luca Sterpone, Carles Ferrer
2017 J jnl
A probe-based SEU detection method for SRAM-based FPGAs.
Microelectron. Reliab.
Luca Sterpone, Luca Boragno
2017 J jnl
An Error-Detection and Self-Repairing Method for Dynamically and Partially Reconfigurable Systems.
IEEE Trans. Computers
Matteo Sonza Reorda, Luca Sterpone, Anees Ullah
2017 J jnl
An FPGA-based dynamically reconfigurable platform for emulation of permanent faults in ASICs.
Microelectron. Reliab.
Anees Ullah, Ernesto Sánchez, Luca Sterpone, Luis Andrés Cardona, Carles Ferrer
2017 C conf
Analysis of radiation-induced cross domain errors in TMR architectures on SRAM-based FPGAs.
IOLTS
Luca Sterpone, Luca Boragno
2017 — conf
Effective Mitigation of Radiation-induced Single Event Transient on Flash-based FPGAs.
ACM Great Lakes Symposium on VLSI
Luca Sterpone, Sarah Azimi, Boyang Du, David Merodio Codinachs, Raoul Grimoldi
2017 J jnl
Evaluation of transient errors in GPGPUs for safety critical applications: An effective simulation-based fault injection environment.
J. Syst. Archit.
Sarah Azimi, Boyang Du, Luca Sterpone
2017 A conf
Fault tolerant electronic system design.
ITC
Boyang Du, Luca Sterpone
2017 — conf
Micro Latch-Up Analysis on Ultra-Nanometer VLSI Technologies: A New Monte Carlo Approach.
ISVLSI
Sarah Azimi, Luca Sterpone
2017 — conf
Online monitoring soft errors in reconfigurable FPGA during radiation test.
I2MTC
Boyang Du, Luca Sterpone
2017 — conf
Reliability evaluation of heterogeneous systems-on-chip for automotive ECUs.
ISIE
Sarah Azimi, Annarita Moramarco, Luca Sterpone
2017 — conf
Self rerouting of dynamically reconfigurable SRAM-based FPGAs.
AHS
Ludovica Bozzoli, Luca Sterpone
2016 — conf
A New Simulation-Based Fault Injection Approach for the Evaluation of Transient Errors in GPGPUs.
ARCS
Sarah Azimi, Boyang Du, Luca Sterpone
2016 B conf
A new EDA flow for the mitigation of SEUs in dynamic reconfigurable FPGAs.
ETS
Boyang Du, Luca Sterpone, David Merodio Codinachs
2016 C conf
An FPGA-based testing platform for the validation of automotive powertrain ECU.
VLSI-SoC
Boyang Du, Luca Sterpone
2016 — conf
Analysis of radiation-induced SEUs on dynamic reconfigurable systems.
ReCoSoC
Luca Sterpone, Luca Boragno, David Merodio Codinachs
2016 — conf
Hybrid soft error mitigation techniques for COTS processor-based systems.
LATS
Eduardo Chielle, Boyang Du, Fernanda Lima Kastensmidt, Sergio Cuenca-Asensi, Luca Sterpone, Matteo Sonza Reorda
2016 J jnl
On the prediction of radiation-induced SETs in flash-based FPGAs.
Microelectron. Reliab.
Sarah Azimi, Boyang Du, Luca Sterpone
2016 J jnl
Online Test of Control Flow Errors: A New Debug Interface-Based Approach.
IEEE Trans. Computers
Boyang Du, Matteo Sonza Reorda, Luca Sterpone, Luis Parra, Marta Portela-García, Almudena Lindoso, Luis Entrena
2016 C conf
Scalable FPGA graph model to detect routing faults.
IOLTS
Luca Sterpone, Gianpiero Cabodi, Sebastiano F. Finocchiaro, Carmelo Loiacono, Francesco Savarese, Boyang Du
2016 J jnl
UA
Integr.
Cinzia Bernardeschi, Luca Cassano, Andrea Domenici, Luca Sterpone
2015 — conf
On the design of highly reliable system-on-chip using dynamically reconfigurable FPGAs.
ReCoSoC
Boyang Du, Luca Sterpone, Lorenzo Venditti, David Merodio Codinachs
2015 J jnl
Radiation-induced single event transients modeling and testing on nanometric flash-based technologies.
Microelectron. Reliab.
Luca Sterpone, Boyang Du, Sarah Azimi
2015 — conf
SET-PAR: Place and Route Tools for the Mitigation of Single Event Transients on Flash-Based FPGAs.
ARC
Luca Sterpone, Boyang Du
2014 C conf
A new solution to on-line detection of Control Flow Errors.
IOLTS
Boyang Du, Matteo Sonza Reorda, Luca Sterpone, Luis Parra, Marta Portela-García, Almudena Lindoso, Luis Entrena
2014 J jnl
ASSESS: A Simulator of Soft Errors in the Configuration Memory of SRAM-Based FPGAs.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Cinzia Bernardeschi, Luca Cassano, Andrea Domenici, Luca Sterpone
2014 B conf
Analysis and mitigation of single event effects on flash-based FPGAS.
ETS
Luca Sterpone, Boyang Du
2014 B conf
Effective emulation of permanent faults in ASICs through dynamically reconfigurable FPGAs.
FPL
Ernesto Sánchez, Luca Sterpone, Anees Ullah
2014 J jnl
Evaluating the radiation sensitivity of GPGPU caches: New algorithms and experimental results.
Microelectron. Reliab.
Davide Sabena, Matteo Sonza Reorda, Luca Sterpone, Paolo Rech, Luigi Carro
2014 B conf
Fault injection and fault tolerance methodologies for assessing device robustness and mitigating against ionizing radiation.
ETS
Dan Alexandrescu, Luca Sterpone, Celia López-Ongil
2014 C conf
Fault injection in GPGPU cores to validate and debug robust parallel applications.
IOLTS
M. De Carvalho, Davide Sabena, Matteo Sonza Reorda, Luca Sterpone, Paolo Rech, Luigi Carro
2014 J jnl
On the Automatic Generation of Optimized Software-Based Self-Test Programs for VLIW Processors.
IEEE Trans. Very Large Scale Integr. Syst.
Davide Sabena, Matteo Sonza Reorda, Luca Sterpone
2014 B conf
Reconfigurable high performance architectures: How much are they ready for safety-critical applications?
ETS
Davide Sabena, Luca Sterpone, Mario Schölzel, Tobias Koal, Heinrich Theodor Vierhaus, S. Wong, Robért Glein, Florian Rittner, C. Stender, Mario Porrmann, Jens Hagemeyer
2014 J jnl
Recovery Time and Fault Tolerance Improvement for Circuits mapped on SRAM-based FPGAs.
J. Electron. Test.
Anees Ullah, Luca Sterpone
2014 C conf
Soft error effects analysis and mitigation in VLIW safety-critical applications.
VLSI-SoC
Davide Sabena, Matteo Sonza Reorda, Luca Sterpone
2014 C conf
Validation of a tool for estimating the effects of soft-errors on modern SRAM-based FPGAs.
IOLTS
Marco Desogus, Luca Sterpone, David Merodio Codinachs
2013 J jnl
A Novel Fault Tolerant and Runtime Reconfigurable Platform for Satellite Payload Processing.
IEEE Trans. Computers
Luca Sterpone, Mario Porrmann, Jens Hagemeyer
2013 B conf
An error-detection and self-repairing method for dynamically and partially reconfigurable systems.
ETS
Matteo Sonza Reorda, Luca Sterpone, Anees Ullah
2013 — conf
Dynamic neutron testing of Dynamically Reconfigurable Processing Modules architecture.
AHS
Luca Sterpone, Davide Sabena, Anees Ullah, Mario Porrmann, Jens Hagemeyer, Jørgen Ilstad
2013 C conf
Exploiting the debug interface to support on-line test of control flow errors.
IOLTS
Boyang Du, Matteo Sonza Reorda, Luca Sterpone, Luis Parra, Marta Portela-García, Almudena Lindoso, Luis Entrena
2013 C conf
On the development of diagnostic test programs for VLIW processors.
VLSI-SoC
Davide Sabena, Matteo Sonza Reorda, Luca Sterpone
2013 — conf
On the evaluation of soft-errors detection techniques for GPGPUs.
IDT
Davide Sabena, Matteo Sonza Reorda, Luca Sterpone, Paolo Rech, Luigi Carro
2013 — conf
On the optimal reconfiguration times for TMR circuits on SRAM based FPGAs.
AHS
Luca Sterpone, Anees Ullah
2013 A conf
On-line testing of permanent radiation effects in reconfigurable systems.
DATE
Luca Cassano, Dario Cozzi, Sebastian Korf, Jens Hagemeyer, Mario Porrmann, Luca Sterpone
2013 — conf
Partition-Based Faults Diagnosis of a VLIW Processor.
VLSI-SoC (Selected Papers)
Davide Sabena, Matteo Sonza Reorda, Luca Sterpone
2013 — conf
Preface.
AHS
Khaled Benkrid, Didier Keymeulen, David Merodio, Michael Newell, Rainer Wansch, Umeshkumar D. Patel, Ahmet T. Erdogan, Niels Hadaschik, Luca Sterpone, Jelle Poupaert, Massimo Violante
2013 J jnl
SEL-UP: A CAD tool for the sensitivity analysis of radiation-induced Single Event Latch-Up.
Microelectron. Reliab.
Luca Sterpone
2013 — conf
Unexcitability analysis of SEus affecting the routing structure of SRAM-based FPGAs.
ACM Great Lakes Symposium on VLSI
Cinzia Bernardeschi, Luca Cassano, Andrea Domenici, Luca Sterpone
2013 — conf
Validation and robustness assessment of an automotive system.
IDT
Marco Desogus, Matteo Sonza Reorda, Luca Sterpone, V. A. Avantaggiati, G. Audisio, Marco Sabatini
2012 C conf
A New Fault Injection Approach for Testing Network-on-Chips.
PDP
Luca Sterpone, Davide Sabena, Matteo Sonza Reorda
2012 A conf
A new SBST algorithm for testing the register file of VLIW processors.
DATE
Davide Sabena, Matteo Sonza Reorda, Luca Sterpone
2012 — conf
A scalable platform for run-time reconfigurable satellite payload processing.
AHS
Jens Hagemeyer, Arne Hilgenstein, Dirk Jungewelter, Dario Cozzi, Carmelo Felicetti, Ulrich Rückert, Sebastian Korf, Markus Koester, Fabio Margaglia, Mario Porrmann, Florian Dittmann, Michael Ditze, Julian Harris, Luca Sterpone, Jørgen Ilstad
2012 — conf
Accurate simulation of SEUs in the configuration memory of SRAM-based FPGAs.
DFT
Cinzia Bernardeschi, Luca Cassano, Andrea Domenici, Luca Sterpone
2012 — conf
High-reliability fault tolerant digital systems in nanometric technologies: Characterization and design methodologies.
DFT
Cristiana Bolchini, Antonio Miele, Chiara Sandionigi, Marco Ottavi, Salvatore Pontarelli, Adelio Salsano, Cecilia Metra, Martin Omaña, Daniele Rossi, Matteo Sonza Reorda, Luca Sterpone, Massimo Violante, Simone Gerardin, Marta Bagatin, Alessandro Paccagnella
2012 — conf
On the Automatic Generation of Software-Based Self-Test Programs for Functional Test and Diagnosis of VLIW Processors.
VLSI-SoC (Selected Papers)
Davide Sabena, Luca Sterpone, Matteo Sonza Reorda
2012 — conf
On the development of Software-Based Self-Test methods for VLIW processors.
DFT
Davide Sabena, Matteo Sonza Reorda, Luca Sterpone
2012 C conf
On the optimized generation of Software-Based Self-Test programs for VLIW processors.
VLSI-SoC
Davide Sabena, Matteo Sonza Reorda, Luca Sterpone
2011 B conf
A Low-Cost Emulation System for Fast Co-verification and Debug.
ETS
Jorge Luis Lagos-Benites, Michelangelo Grosso, Luca Sterpone, Matteo Sonza Reorda, G. Audisio, M. Pipponzi, Marco Sabatini
2011 A conf
A new reconfigurable clock-gating technique for low power SRAM-based FPGAs.
DATE
Luca Sterpone, Luigi Carro, Debora Matos, Stephan Wong, F. Fakhar
2011 — conf
Analysis of SEU effects in partially reconfigurable SoPCs.
AHS
Luca Sterpone, Fabio Margaglia, Markus Köster, Jens Hagemeyer, Mario Porrmann
2011 J jnl
Coping With the Obsolescence of Safety- or Mission-Critical Embedded Systems Using FPGAs.
IEEE Trans. Ind. Electron.
Hipólito Guzmán-Miranda, Luca Sterpone, Massimo Violante, Miguel A. Aguirre, Manuel Gutiérrez-Rizo
2011 C conf
Fault injection analysis of transient faults in clustered VLIW processors.
DDECS
Luca Sterpone, Davide Sabena, Salvatore Campagna, Matteo Sonza Reorda
2011 — book
Reconfigurable Field Programmable Gate Arrays for Mission-Critical Applications.
Niccolò Battezzati, Luca Sterpone, Massimo Violante
2010 — conf
A New Soft-Error Resilient Voltage-Mode Quaternary Latch.
DFT
Eduardo Luis Rhod, Luca Sterpone, Luigi Carro
2010 J jnl
A New Timing Driven Placement Algorithm for Dependable Circuits on SRAM-based FPGAs.
ACM Trans. Reconfigurable Technol. Syst.
Luca Sterpone
2010 A conf
A new placement algorithm for the mitigation of multiple cell upsets in SRAM-based FPGAs.
DATE
Luca Sterpone, Niccolò Battezzati
2010 C conf
A new software tool for static analysis of SET sensitiveness in Flash-based FPGAs.
VLSI-SoC
Niccolò Battezzati, Luca Sterpone, Massimo Violante, Filomena Decuzzi
2010 C conf
A novel scalable and reconfigurable emulation platform for embedded systems verification.
ISCAS
M. Di Marzio, Michelangelo Grosso, Matteo Sonza Reorda, Luca Sterpone, G. Audisio, Marco Sabatini
2010 B conf
An integrated flow for the design of hardened circuits on SRAM-based FPGAs.
ETS
Cristiana Bolchini, Antonio Miele, Chiara Sandionigi, Niccolò Battezzati, Luca Sterpone, Massimo Violante
2010 C conf
On the mitigation of SET broadening effects in integrated circuits.
DDECS
Luca Sterpone, Niccolò Battezzati
2009 J jnl
A Novel Dual-Core Architecture for the Analysis of DNA Microarray Images.
IEEE Trans. Instrum. Meas.
Luca Sterpone
2009 — conf
A new RC design for mixed-grain based dynamically reconfigurable architectures.
ICECS
Eduardo Luis Rhod, Luca Sterpone, Luigi Carro
2009 A conf
A study of the Single Event Effects impact on functional mapping within Flash-based FPGAs.
DATE
Francesco Abate, Luca Sterpone, Massimo Violante, Fernanda Lima Kastensmidt
2009 — book
Electronics System Design Techniques for Safety Critical Applications
Luca Sterpone
2009 B conf
Soft errors in Flash-based FPGAs: Analysis methodologies and first results.
FPL
Niccolò Battezzati, Filomena Decuzzi, Luca Sterpone, Massimo Violante
2009 — conf
Timing Driven Placement for Fault Tolerant Circuits Implemented on SRAM-Based FPGAs.
ARC
Luca Sterpone
2008 — conf
A Novel Design Flow for the Performance Optimization of Fault Tolerant Circuits on SRAM-based FPGA's.
AHS
Luca Sterpone, Niccolò Battezzati
2008 C conf
A graph-based representation of Gene Expression profiles in DNA microarrays.
CIBCB
Alfredo Benso, Stefano Di Carlo, Gianfranco Politano, Luca Sterpone
2008 — conf
A new placement algorithm for the optimization of fault tolerant circuits on reconfigurable devices.
WREFT@CF
Luca Sterpone, Niccolò Battezzati, Massimo Violante
2008 C conf
Differential gene expression graphs: A data structure for classification in DNA microarrays.
BIBE
Alfredo Benso, Stefano Di Carlo, Gianfranco Politano, Luca Sterpone
2008 — ch.
FPGA PAL Design Tools.
Wiley Encyclopedia of Computer Science and Engineering
Luca Sterpone
2008 C conf
On the Evaluation of Radiation-Induced Transient Faults in Flash-Based FPGAs.
IOLTS
Niccolò Battezzati, Simone Gerardin, Andrea Manuzzato, Alessandro Paccagnella, Sana Rezgui, Luca Sterpone, Massimo Violante
2008 A conf
On the design of tunable fault tolerant circuits on SRAM-based FPGAs for safety critical applications.
DATE
Luca Sterpone, M. A. Aguirre, Jonathan Noel Tombs, Hipólito Guzmán-Miranda
2008 J jnl
Software and Hardware Techniques for SEU Detection in IP Processors.
J. Electron. Test.
Cristiana Bolchini, Antonio Miele, Fabio Rebaudengo, Fabio Salice, Donatella Sciuto, Luca Sterpone, Massimo Violante
2007 — conf
A new decompression system for the configuration process of SRAM-based FPGAS.
ACM Great Lakes Symposium on VLSI
Luca Sterpone, Massimo Violante
2007 — conf
A new hardware architecture for performing the gridding of DNA microarray images.
ACM Great Lakes Symposium on VLSI
Luca Sterpone, Massimo Violante
2007 C conf
An Experimental Analysis of SEU Sensitiveness on System Knowledge-based Hardening Techniques.
DDECS
Oscar Ruano, Pilar Reyes, Juan Antonio Maestro, Luca Sterpone, Pedro Reviriego
2007 J jnl
Evaluating Different Solutions to Design Fault Tolerant Systems with SRAM-based FPGAs.
J. Electron. Test.
Luca Sterpone, Matteo Sonza Reorda, Massimo Violante, Fernanda Lima Kastensmidt, Luigi Carro
2007 J jnl
On the Optimal Design of Triple Modular Redundancy Logic for SRAM-based FPGAs
CoRR
Fernanda Lima Kastensmidt, Luca Sterpone, Luigi Carro, Matteo Sonza Reorda
2007 — conf
Optimization of Self Checking FIR filters by means of Fault Injection Analysis.
DFT
Salvatore Pontarelli, Luca Sterpone, Gian Carlo Cardarilli, Marco Re, Matteo Sonza Reorda, Adelio Salsano, Massimo Violante
2007 C conf
Self Checking Circuit Optimization by means of Fault Injection Analysis: A Case Study on Reed Solomon Decoders.
IOLTS
Salvatore Pontarelli, Luca Sterpone, Gian Carlo Cardarilli, Marco Re, Matteo Sonza Reorda, Adelio Salsano, Massimo Violante
2007 — conf
Sensitivity Evaluation of TMR-Hardened Circuits to Multiple SEUs Induced by Alpha Particles in Commercial SRAM-Based FPGAs.
DFT
Andrea Manuzzato, Paolo Rech, Simone Gerardin, Alessandro Paccagnella, Luca Sterpone, Massimo Violante
2007 B conf
Static and Dynamic Analysis of SEU Effects in SRAM-Based FPGAs.
ETS
Luca Sterpone, Massimo Violante
2006 — conf
A Fault Injection Environment for SoPC's Embedded Microprocessors.
LATW
Marta Portela-García, Luca Sterpone, Celia López-Ongil, Matteo Sonza Reorda, Massimo Violante
2006 J jnl
A New Reliability-Oriented Place and Route Algorithm for SRAM-Based FPGAs.
IEEE Trans. Computers
Luca Sterpone, Massimo Violante
2006 — conf
A new approach to compress the configuration information of programmable devices.
DATE Designers' Forum
Maurizio Martina, Guido Masera, Andrea Molino, Fabrizio Vacca, Luca Sterpone, Massimo Violante
2006 — conf
An experimental analysis of a new mixed grain-based dynamically reconfigurable architecture.
ICECS
Luca Sterpone
2006 — conf
Combined software and hardware techniques for the design of reliable IP processors.
DFT
Maurizio Rebaudengo, Luca Sterpone, Massimo Violante, Cristiana Bolchini, Antonio Miele, Donatella Sciuto
2006 C conf
Dependability Evaluation of Transient Fault Effects in Reconfigurable Compute Fabric Devices.
IOLTS
Luca Sterpone, Massimo Violante
2006 B conf
Fault Injection-based Reliability Evaluation of SoPCs.
ETS
Matteo Sonza Reorda, Luca Sterpone, Massimo Violante, Marta Portela-García, Celia López-Ongil, Luis Entrena
2006 J jnl
Hardening FPGA-based Systems Against SEUs: A New Design Methodology.
J. Comput.
Luca Sterpone, Massimo Violante
2006 C conf
ReCoM: A New Reconfigurable Compute Fabric Architecture for Computation-Intensive Applications.
DDECS
Luca Sterpone, Massimo Violante
2005 — conf
A design flow for protecting FPGA-based systems against single event upsets.
DFT
Luca Sterpone, Massimo Violante
2005 C conf
Efficient Estimation of SEU Effects in SRAM-Based FPGAs.
IOLTS
Matteo Sonza Reorda, Luca Sterpone, Massimo Violante
2005 B conf
Multiple errors produced by single upsets in FPGA configuration memory: a possible solution.
ETS
Matteo Sonza Reorda, Luca Sterpone, Massimo Violante
2005 A conf
New evolutionary techniques for test-program generation for complex microprocessor cores.
GECCO
Ernesto Sánchez, Massimiliano Schillaci, Matteo Sonza Reorda, Giovanni Squillero, Luca Sterpone, Massimo Violante
2005 A conf
On the Optimal Design of Triple Modular Redundancy Logic for SRAM-based FPGAs.
DATE
Fernanda Lima Kastensmidt, Luca Sterpone, Luigi Carro, Matteo Sonza Reorda
2004 C conf
On the Evaluation of SEU Sensitiveness in SRAM-Based FPGAs.
IOLTS
Paolo Bernardi, Matteo Sonza Reorda, Luca Sterpone, Massimo Violante