Luca Macchiarulo

41 papers A* 3A 9B 1C 1Misc 1Journal 12Unranked 14
YearRankTypeTitle / Venue / Authors
2026 J jnl
Machine Learning on Heterogeneous, Edge, and Quantum Hardware for Particle Physics (ML-HEQUPP).
CoRR
Julia Gonski, Jenni Ott, Shiva Abbaszadeh, Sagar Addepalli, Matteo Cremonesi, Jennet Dickinson, Giuseppe Di Guglielmo, Erdem Yigit Ertorer, Lindsey Gray, Ryan Herbst, Christian Herwig, Tae Min Hong, Benedikt Maier, Maryam Bayat Makou, David Miller, Mark S. Neubauer, Cristián Peña, Dylan Rankin, Seon-Hee Seo, Giordon Stark, Alexander Tapper, Audrey Corbeil Therrien, Ioannis Xiotidis, Keisuke Yoshihara, G. Abarajithan, Nural Akchurin, Carlos Argüelles, Saptaparna Bhattacharya, Lorenzo Borella, Christian Boutan, Tom Braine, James Brau, Martin Breidenbach, Antonio Chahine, Talal Ahmed Chowdhury, Yuan-Tang Chou, Seokju Chung, Alberto Coppi, Mariarosaria D'Alfonso, Abhilasha Dave, Chance DeSmet, Angela Di Fulvio, Karri DiPetrillo, Javier Duarte, Auralee Edelen, Jan Eysermans, Yongbin Feng, Emmett Forrestel, Dolores Garcia, Loredana Gastaldo, Julián García Pardiñas, Lino Gerlach, Loukas Gouskos, Katya Govorkova, Carl Grace, Christopher Grant, Philip Harris, Ciaran Hasnip, Timon Heim, Abraham Holtermann, Gian Michele Innocenti, Koji Ishidoshiro, Miaochen Jin, Jyothisraj Johnson, Stephen Jones, Andreas Jung, Georgia Karagiorgi, Ryan Kastner, Nicholas Kamp, Doojin Kim, Kyoungchul Kong, Katie Kudela, Jelena Lalic, Bo-Cheng Lai, Yun-Tsung Lai, Tommy Lam, Jeffrey Lazar, Aobo Li, Zepeng Li, Haoyun Liu, Vladimir Loncar, Luca Macchiarulo, Christopher Madrid, Zhenghua Ma, Prashansa Mukim, Victoria Nguyen, Sungbin Oh, Isobel Ojalvo, Hideyoshi Ozaki, Simone Pagan Griso, Myeonghun Park, Christoph Paus, Santosh Parajuli, Benjamin Parpillon, Sara Pozzi, Ema Puljak
2011 A conf
A jumper insertion algorithm under antenna ratio and timing constraints.
ICCAD
Xin Gao, Luca Macchiarulo
2010 J jnl
Digital Heart-Rate Variability Parameter Monitoring and Assessment ASIC.
IEEE Trans. Biomed. Circuits Syst.
Wansuree Massagram, Noah Hafner, Mingqi Chen, Luca Macchiarulo, Victor Lubecke, Olga Boric-Lubecke
2010 A conf
Enhancing double-patterning detailed routing with lazy coloring and within-path conflict avoidance.
DATE
Xin Gao, Luca Macchiarulo
2009 J jnl
A Case Study for NoC-Based Homogeneous MPSoC Architectures.
IEEE Trans. Very Large Scale Integr. Syst.
Sergio Tota, Mario R. Casu, Massimo Ruo Roch, Luca Macchiarulo, Maurizio Zamboni
2009 — conf
Adaptive Latency Insensitive Protocols and Elastic Circuits with Early Evaluation: A Comparative Analysis.
FMGALS@DATE
Mario R. Casu, Luca Macchiarulo
2007 J jnl
Adaptive Latency-Insensitive Protocols.
IEEE Des. Test Comput.
Mario R. Casu, Luca Macchiarulo
2006 J jnl
Floorplanning With Wire Pipelining in Adaptive Communication Channels.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Mario R. Casu, Luca Macchiarulo
2006 — conf
Fully-Integrated Heart Rate Variability Monitoring System with an Efficient Memory.
EMBC
Xiaoyue Wang, Mingqi Chen, Luca Macchiarulo, Olga Boric-Lubecke
2006 — conf
Implementation analysis of NoC: a MPSoC trace-driven approach.
ACM Great Lakes Symposium on VLSI
Sergio Tota, Mario R. Casu, Luca Macchiarulo
2006 — conf
Using Existing Digital Tools for Efficient Metabolic Pathway Simulations.
EMBC
Luca Macchiarulo
2005 A conf
A New System Design Methodology for Wire Pipelined SoC.
DATE
Mario R. Casu, Luca Macchiarulo
2005 — conf
Floorplan assisted data rate enhancement through wire pipelining: a real assessment.
ISPD
Mario R. Casu, Luca Macchiarulo
2005 J jnl
Throughput-driven floorplanning with wire pipelining.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Mario R. Casu, Luca Macchiarulo
2004 — conf
A comparison between mask- and field-programmable routing structures on industrial FPGA architectures.
ACM Great Lakes Symposium on VLSI
Luca Macchiarulo, Consolato F. Caccamo, Davide Pandini
2004 A* conf
A new approach to latency insensitive design.
DAC
Mario R. Casu, Luca Macchiarulo
2004 — conf
Floorplanning for throughput.
ISPD
Mario R. Casu, Luca Macchiarulo
2004 A conf
Issues in Implementing Latency Insensitive Protocols.
DATE
Mario R. Casu, Luca Macchiarulo
2004 C conf
On-Chip Transparent Wire Pipelining.
ICCD
Mario R. Casu, Luca Macchiarulo
2004 J jnl
Pipelining Sequential Circuits with Wave Steering.
IEEE Trans. Computers
Luca Macchiarulo, Shih-Min Shu, Malgorzata Marek-Sadowska
2003 J jnl
New techniques for efficiently assessing reliability of SOCs.
Microelectron. J.
Pierluigi Civera, Luca Macchiarulo, Maurizio Rebaudengo, Matteo Sonza Reorda, Massimo Violante
2003 J jnl
PITIA: an FPGA for throughput-intensive applications.
IEEE Trans. Very Large Scale Integr. Syst.
Amit Singh, Arindam Mukherjee, Luca Macchiarulo, Malgorzata Marek-Sadowska
2002 — conf
A Simplified Gate-Level Fault Model for Crosstalk Effects Analysis.
DFT
Pierluigi Civera, Luca Macchiarulo, Massimo Violante
2002 J jnl
An FPGA-Based Approach for Speeding-Up Fault Injection Campaigns on Safety-Critical Circuits.
J. Electron. Test.
Pierluigi Civera, Luca Macchiarulo, Maurizio Rebaudengo, Matteo Sonza Reorda, Massimo Violante
2002 — conf
Enhanced clustered voltage scaling for low power.
ACM Great Lakes Symposium on VLSI
Monica Donno, Luca Macchiarulo, Alberto Macii, Enrico Macii, Massimo Poncino
2002 J jnl
Layout-driven memory synthesis for embedded systems-on-chip.
IEEE Trans. Very Large Scale Integr. Syst.
Luca Benini, Luca Macchiarulo, Alberto Macii, Massimo Poncino
2002 A conf
Wire Placement for Crosstalk Energy Minimization in Address Buses.
DATE
Luca Macchiarulo, Enrico Macii, Massimo Poncino
2001 — conf
Exploiting FPGA for Accelerating Fault Injection Experiments.
IOLTW
Pierluigi Civera, Luca Macchiarulo, Maurizio Rebaudengo, Matteo Sonza Reorda, Massimo Violante
2001 — conf
Exploiting FPGA-Based Techniques for Fault Injection Campaigns on VLSI Circuits .
DFT
Pierluigi Civera, Luca Macchiarulo, Maurizio Rebaudengo, Matteo Sonza Reorda, Massimo Violante
2001 B conf
FPGA-Based Fault Injection Techniques for Fast Evaluation of Fault Tolerance in VLSI Circuits.
FPL
Pierluigi Civera, Luca Macchiarulo, Maurizio Rebaudengo, Matteo Sonza Reorda, Massimo Violante
2001 — conf
FPGA-Based Fault Injection for Microprocessor Systems.
Asian Test Symposium
Pierluigi Civera, Luca Macchiarulo, Maurizio Rebaudengo, Matteo Sonza Reorda, Massimo Violante
2001 A* conf
From Architecture to Layout: Partitioned Memory Synthesis for Embedded Systems-on-Chip.
DAC
Luca Benini, Luca Macchiarulo, Alberto Macii, Enrico Macii, Massimo Poncino
2001 A conf
Low-energy for deep-submicron address buses.
ISLPED
Luca Macchiarulo, Enrico Macii, Massimo Poncino
2001 A conf
On-the-fly layout generation for PTL macrocells.
DATE
Luca Macchiarulo, Luca Benini, Enrico Macii
2000 J jnl
A Comment on 'Graph-Based Algorithm for Boolean Function Manipulation'.
IEEE Trans. Computers
Elena Dubrova, Luca Macchiarulo
2000 A conf
A novel high throughput reconfigurable FPGA architecture.
FPGA
Amit Singh, Luca Macchiarulo, Arindam Mukherjee, Malgorzata Marek-Sadowska
2000 A conf
Wave Steered FSMs.
DATE
Luca Macchiarulo, Shih-Ming Shu, Malgorzata Marek-Sadowska
2000 A* conf
Wave-steering one-hot encoded FSMs.
DAC
Luca Macchiarulo, Malgorzata Marek-Sadowska
1999 Misc conf
Functional Decomposition through Structural Analysis of Decision Diagrams - the Binary and Multiple-Valued Cases.
VLSI Design
Luca Macchiarulo, Pierluigi Civera
1998 — conf
Artificial Neural Networks for Motion Emulation in Virtual Environments.
CAPTECH
Y. Bellan, Mario Costa, Giancarlo Ferrigno, Fabrizio Lombardi, Luca Macchiarulo, Alfonso Montuori, Eros Pasero, Camilla Rigotti
1998 — conf
Ternary Decision Diagrams with Inverted Edges and Cofactoring - An Application to Discrete Neural Networks Synthesis.
ISMVL
Luca Macchiarulo, Pierluigi Civera