Luca G. Amarù

24 papers A* 7A 8Journal 4Unranked 5

Year	Rank	Type	Title / Venue / Authors
2026	J	`jnl`	Scalable Sequential Logic Synthesis Using Observability Don't Care Conditions. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Dewmini Sudara Marakkalage, Eleonora Testa, Giulia Meuli, Walter Lau Neto, Alan Mishchenko, Giovanni De Micheli, Luca G. Amarù
2025	—	`conf`	ML-Inspired Logic Synthesis: Improving Multiplier Circuits. MLCAD Yukio Miyasaka, Walter Lau Neto, Eleonora Testa, Anika Prasad, Michael Shuster, Reto Zimmermann, Patrick Vuillod, Alan Mishchenko, John Wawrzynek, Luca G. Amarù
2024	A	`conf`	Scalable Sequential Optimization Under Observability Don't Cares. DATE Dewmini Sudara Marakkalage, Eleonora Testa, Walter Lau Neto, Alan Mishchenko, Giovanni De Micheli, Luca G. Amarù
2023	J	`jnl`	Scalable Sequential Optimization Under Observability Don't Cares. CoRR Dewmini Sudara Marakkalage, Eleonora Testa, Walter Lau Neto, Alan Mishchenko, Giovanni De Micheli, Luca G. Amarù
2022	A*	`conf`	Improving LUT-based optimization for ASICs. DAC Walter Lau Neto, Luca G. Amarù, Vinicius Possani, Patrick Vuillod, Jiong Luo, Alan Mishchenko, Pierre-Emmanuel Gaillardon
2022	A	`conf`	Majority-based Design Flow for AQFP Superconducting Family. DATE Giulia Meuli, Vinicius N. Possani, Rajinder Singh, Siang-Yun Lee, Alessandro Tempia Calvino, Dewmini Sudara Marakkalage, Patrick Vuillod, Luca G. Amarù, Scott Chase, Jamil Kawa, Giovanni De Micheli
2021	A*	`conf`	Deep Integration of Circuit Simulator and SAT Solver. DAC He-Teng Zhang, Jie-Hong R. Jiang, Luca G. Amarù, Alan Mishchenko, Robert K. Brayton
2021	—	`conf`	Read your Circuit: Leveraging Word Embedding to Guide Logic Optimization. ASP-DAC Walter Lau Neto, Matheus Trevisan Moreira, Luca G. Amarù, Cunxi Yu, Pierre-Emmanuel Gaillardon
2021	A*	`conf`	SLAP: A Supervised Learning Approach for Priority Cuts Technology Mapping. DAC Walter Lau Neto, Matheus T. Moreira, Yingjie Li, Luca G. Amarù, Cunxi Yu, Pierre-Emmanuel Gaillardon
2020	A	`conf`	A Logic Synthesis Toolbox for Reducing the Multiplicative Complexity in Logic Networks. DATE Eleonora Testa, Mathias Soeken, Heinz Riener, Luca G. Amarù, Giovanni De Micheli
2020	J	`jnl`	A Logic Synthesis Toolbox for Reducing the Multiplicative Complexity in Logic Networks. IACR Cryptol. ePrint Arch. Eleonora Testa, Mathias Soeken, Heinz Riener, Luca G. Amarù, Giovanni De Micheli
2020	A	`conf`	A Scalable Mixed Synthesis Framework for Heterogeneous Networks. DATE Max Austin, Scott Temple, Walter Lau Neto, Luca G. Amarù, Xifan Tang, Pierre-Emmanuel Gaillardon
2020	J	`jnl`	Extending Boolean Methods for Scalable Logic Synthesis. IEEE Access Eleonora Testa, Luca G. Amarù, Mathias Soeken, Alan Mishchenko, Patrick Vuillod, Pierre-Emmanuel Gaillardon, Giovanni De Micheli
2020	A*	`conf`	SAT-Sweeping Enhanced for Logic Synthesis. DAC Luca G. Amarù, Felipe S. Marranghello, Eleonora Testa, Christopher Casares, Vinicius N. Possani, Jiong Luo, Patrick Vuillod, Alan Mishchenko, Giovanni De Micheli
2019	—	`conf`	Improving Logic Optimization in Sequential Circuits using Majority-inverter Graphs. ISVLSI Walter Lau Neto, Xifan Tang, Max Austin, Luca G. Amarù, Pierre-Emmanuel Gaillardon
2019	A	`conf`	LSOracle: a Logic Synthesis Framework Driven by Artificial Intelligence: Invited Paper. ICCAD Walter Lau Neto, Max Austin, Scott Temple, Luca G. Amarù, Xifan Tang, Pierre-Emmanuel Gaillardon
2019	—	`conf`	Logic Optimization of Majority-Inverter Graphs. MBMV Heinz Riener, Eleonora Testa, Winston Haaswijk, Alan Mishchenko, Luca G. Amarù, Giovanni De Micheli, Mathias Soeken
2019	A*	`conf`	Reducing the Multiplicative Complexity in Logic Networks for Cryptography and Security Applications. DAC Eleonora Testa, Mathias Soeken, Luca G. Amarù, Giovanni De Micheli
2019	A	`conf`	Scalable Boolean Methods in a Modern Synthesis Flow. DATE Eleonora Testa, Luca G. Amarù, Mathias Soeken, Alan Mishchenko, Patrick Vuillod, Jiong Luo, Christopher Casares, Pierre-Emmanuel Gaillardon, Giovanni De Micheli
2019	A*	`conf`	Scalable Generic Logic Synthesis: One Approach to Rule Them All. DAC Heinz Riener, Eleonora Testa, Winston Haaswijk, Alan Mishchenko, Luca G. Amarù, Giovanni De Micheli, Mathias Soeken
2018	A*	`conf`	Canonical computation without canonical representation. DAC Alan Mishchenko, Robert K. Brayton, Ana Petkovska, Mathias Soeken, Luca G. Amarù, Antun Domic
2018	A	`conf`	Majority logic synthesis. ICCAD Luca G. Amarù, Eleonora Testa, Miguel Couceiro, Odysseas Zografos, Giovanni De Micheli, Mathias Soeken
2018	—	`conf`	Size Optimization of MIGs with an Application to QCA and STMG Technologies. NANOARCH Heinz Riener, Eleonora Testa, Luca G. Amarù, Mathias Soeken, Giovanni De Micheli
2018	A	`conf`	Technology-aware logic synthesis for ReRAM based in-memory computing. DATE Debjyoti Bhattacharjee, Luca G. Amarù, Anupam Chattopadhyay