Luca Colagrande

24 papers A* 2A 3Journal 16Unranked 3
YearRankTypeTitle / Venue / Authors
2026 J jnl
A Lightweight High-Throughput Collective-Capable NoC for Large-Scale ML Accelerators.
CoRR
Luca Colagrande, Lorenzo Leone, Chen Wu, Tim Fischer, Raphael Roth, Luca Benini
2026 J jnl
Late Breaking Results: Boosting Efficient Dual-Issue Execution on Lightweight RISC-V Cores.
CoRR
Luca Colagrande, Luca Benini
2025 — conf
A Multicast-Capable AXI Crossbar for Many-core Machine Learning Accelerators.
AICAS
Luca Colagrande, Luca Benini
2025 J jnl
A Multicast-Capable AXI Crossbar for Many-core Machine Learning Accelerators.
CoRR
Luca Colagrande, Luca Benini
2025 A* conf
Dual-Issue Execution of Mixed Integer and Floating-Point Workloads on Energy-Efficient In-Order RISC-V Cores.
DAC
Luca Colagrande, Luca Benini
2025 J jnl
Dual-Issue Execution of Mixed Integer and Floating-Point Workloads on Energy-Efficient In-Order RISC-V Cores.
CoRR
Luca Colagrande, Luca Benini
2025 — conf
FlatAttention: Dataflow and Fabric Collectives Co-Optimization for Efficient Multi-Head Attention on Tile-Based Many-PE Accelerators.
ISVLSI
Chi Zhang, Luca Colagrande, Renzo Andri, Thomas Benz, Gamze Islamoglu, Alessandro Nadalini, Francesco Conti, Yawei Li, Luca Benini
2025 J jnl
FlatAttention: Dataflow and Fabric Collectives Co-Optimization for Efficient Multi-Head Attention on Tile-Based Many-PE Accelerators.
CoRR
Chi Zhang, Luca Colagrande, Renzo Andri, Thomas Benz, Gamze Islamoglu, Alessandro Nadalini, Francesco Conti, Yawei Li, Luca Benini
2025 A conf
Late Breaking Results: A RISC-V ISA Extension for Chaining in Scalar Processors.
DATE
Luca Colagrande, Jayanth Jonnalagadda, Luca Benini
2025 J jnl
Late Breaking Results: A RISC-V ISA Extension for Chaining in Scalar Processors.
CoRR
Luca Colagrande, Jayanth Jonnalagadda, Luca Benini
2025 J jnl
Occamy: A 432-Core Dual-Chiplet Dual-HBM2E 768-DP-GFLOP/s RISC-V System for 8-to-64-bit Dense and Sparse Computing in 12-nm FinFET.
IEEE J. Solid State Circuits
Paul Scheffler, Thomas Benz, Viviane Potocnik, Tim Fischer, Luca Colagrande, Nils Wistoff, Yichao Zhang, Luca Bertaccini, Gianmarco Ottavi, Manuel Eggimann, Matheus A. Cavalcante, Gianna Paulin, Frank K. Gürkaynak, Davide Rossi, Luca Benini
2025 J jnl
Occamy: A 432-Core Dual-Chiplet Dual-HBM2E 768-DP-GFLOP/s RISC-V System for 8-to-64-bit Dense and Sparse Computing in 12nm FinFET.
CoRR
Paul Scheffler, Thomas Benz, Viviane Potocnik, Tim Fischer, Luca Colagrande, Nils Wistoff, Yichao Zhang, Luca Bertaccini, Gianmarco Ottavi, Manuel Eggimann, Matheus A. Cavalcante, Gianna Paulin, Frank K. Gürkaynak, Davide Rossi, Luca Benini
2025 J jnl
Taming Offload Overheads in a Massively Parallel Open-Source RISC-V MPSoC: Analysis and Optimization.
CoRR
Luca Colagrande, Luca Benini
2025 J jnl
Taming Offload Overheads in a Massively Parallel Open-Source RISC-V MPSoC: Analysis and Optimization.
IEEE Trans. Parallel Distributed Syst.
Luca Colagrande, Luca Benini
2025 A conf
Towards Zero-Stall Matrix Multiplication on Energy-Efficient RISC-V Clusters for Machine Learning Acceleration.
ISLPED
Luca Colagrande, Lorenzo Leone, Maximilian Coco, Andrei Deaconeasa, Luca Benini
2025 J jnl
Towards Zero-Stall Matrix Multiplication on Energy-Efficient RISC-V Clusters for Machine Learning Acceleration.
CoRR
Luca Colagrande, Lorenzo Leone, Maximilian Coco, Andrei Deaconeasa, Luca Benini
2024 — conf
Occamy: A 432-Core 28.1 DP-GFLOP/s/W 83% FPU Utilization Dual-Chiplet, Dual-HBM2E RISC-V-Based Accelerator for Stencil and Sparse Linear Algebra Computations with 8-to-64-bit Floating-Point Support in 12nm FinFET.
VLSI Technology and Circuits
Gianna Paulin, Paul Scheffler, Thomas Benz, Matheus A. Cavalcante, Tim Fischer, Manuel Eggimann, Yichao Zhang, Nils Wistoff, Luca Bertaccini, Luca Colagrande, Gianmarco Ottavi, Frank K. Gürkaynak, Davide Rossi, Luca Benini
2024 J jnl
Occamy: A 432-Core 28.1 DP-GFLOP/s/W 83% FPU Utilization Dual-Chiplet, Dual-HBM2E RISC-V-based Accelerator for Stencil and Sparse Linear Algebra Computations with 8-to-64-bit Floating-Point Support in 12nm FinFET.
CoRR
Gianna Paulin, Paul Scheffler, Thomas Benz, Matheus A. Cavalcante, Tim Fischer, Manuel Eggimann, Yichao Zhang, Nils Wistoff, Luca Bertaccini, Luca Colagrande, Gianmarco Ottavi, Frank K. Gürkaynak, Davide Rossi, Luca Benini
2024 J jnl
Optimizing Foundation Model Inference on a Many-Tiny-Core Open-Source RISC-V Platform.
IEEE Trans. Circuits Syst. Artif. Intell.
Viviane Potocnik, Luca Colagrande, Tim Fischer, Luca Bertaccini, Daniele Jahier Pagliari, Alessio Burrello, Luca Benini
2024 J jnl
Optimizing Foundation Model Inference on a Many-tiny-core Open-source RISC-V Platform.
CoRR
Viviane Potocnik, Luca Colagrande, Tim Fischer, Luca Bertaccini, Daniele Jahier Pagliari, Alessio Burrello, Luca Benini
2024 A conf
Optimizing Offload Performance in Heterogeneous MPSoCs.
DATE
Luca Colagrande, Luca Benini
2024 J jnl
Optimizing Offload Performance in Heterogeneous MPSoCs.
CoRR
Luca Colagrande, Luca Benini
2024 A* conf
SARIS: Accelerating Stencil Computations on Energy-Efficient RISC-V Compute Clusters with Indirect Stream Registers.
DAC
Paul Scheffler, Luca Colagrande, Luca Benini
2024 J jnl
SARIS: Accelerating Stencil Computations on Energy-Efficient RISC-V Compute Clusters with Indirect Stream Registers.
CoRR
Paul Scheffler, Luca Colagrande, Luca Benini