Luca Cassano - RankMe

71 papers A 7B 3C 11Journal 26Unranked 20

Year	Rank	Type	Title / Venue / Authors
2026	J	`jnl`	Benchmark Suite for Resilience Assessment of Deep Learning Models. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Cristiana Bolchini, Alberto Bosio, Luca Cassano, Antonio Miele, Salvatore Pappalardo, Dario Passarello, Annachiara Ruospo, Ernesto Sánchez, Matteo Sonza Reorda, Vittorio Turco
2025	A	`conf`	A Benchmark Suite to Evaluate DNN's Resilience. ITC Cristiana Bolchini, Alberto Bosio, Luca Cassano, Antonio Miele, Salvatore Pappalardo, Dario Passariello, Annachiara Ruospo, Ernesto Sánchez, Matteo Sonza Reorda, Vittorio Turco
2025	C	`conf`	S4V: A Benchmark Suite of Transient Execution Attacks for RISC-V Processors. DDECS Elia Lazzeri, Matteo Colella, Gianluca Furano, Luca Cassano
2024	—	`conf`	An Experimental Comparison of RISC-V Processors: Performance, Power, Area and Security - Special Session Paper-. DFT Elia Lazzeri, Bruno E. Forlin, Gianluca Furano, Marco Ottavi, Luca Cassano
2024	B	`conf`	Cross-Layer Reliability Analysis of NVDLA Accelerators: Exploring the Configuration Space. ETS Alessandro Veronesi, Alessandro Nazzari, Dario Passarello, Milos Krstic, Michele Favalli, Luca Cassano, Antonio Miele, Davide Bertozzi, Cristiana Bolchini
2024	A	`conf`	Lightweight Instrumentation for Accurate Performance Monitoring in RTOSes. DATE Bruno Endres Forlin, Kuan-Hsun Chen, Nikolaos Alachiotis, Luca Cassano, Marco Ottavi
2024	—	`conf`	Range Restriction to Harden CNNs Against Hardware Faults: A Broad Empirical Analysis. DFT Cristiana Bolchini, Luca Cassano, Antonio Miele, Dario Passarella
2024	J	`jnl`	Resilience of deep learning applications: A systematic literature review of analysis and hardening techniques. Comput. Sci. Rev. Cristiana Bolchini, Luca Cassano, Antonio Miele
2023	—	`conf`	Analyzing the Reliability of Alternative Convolution Implementations for Deep Learning Applications. DFT Cristiana Bolchini, Luca Cassano, Antonio Miele, Alessandro Nazzari, Dario Passarello
2023	—	`conf`	Built-in Software Obfuscation for Protecting Microprocessors against Hardware Trojan Horses. DFT Alessandro Palumbo, Marco Ottavi, Luca Cassano
2023	J	`jnl`	Fast and Accurate Error Simulation for CNNs Against Soft Errors. IEEE Trans. Computers Cristiana Bolchini, Luca Cassano, Antonio Miele, Alessandro Toschi
2023	—	`ed.`	IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, DFT 2023, Juan-Les-Pins, France, October 3-5, 2023 DFT Luca Cassano, Mihalis Psarakis, Marcello Traiola, Alberto Bosio
2023	—	`conf`	Improving the Detection of Hardware Trojan Horses in Microprocessors via Hamming Codes. DFT Alessandro Palumbo, Luca Cassano, Pedro Reviriego, Marco Ottavi
2023	J	`jnl`	Optimizing the Use of Behavioral Locking for High-Level Synthesis. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Christian Pilato, Luca Collini, Luca Cassano, Donatella Sciuto, Siddharth Garg, Ramesh Karri
2023	J	`jnl`	Resilience of Deep Learning applications: a systematic survey of analysis and hardening techniques. CoRR Cristiana Bolchini, Luca Cassano, Antonio Miele
2023	C	`conf`	Towards Dependable RISC-V Cores for Edge Computing Devices. IOLTS Pegdwende Romaric Nikiema, Alessandro Palumbo, Allan Aasma, Luca Cassano, Angeliki Kritikakou, Ari Kulmala, Jari Lukkarila, Marco Ottavi, Rafail Psiakis, Marcello Traiola
2022	J	`jnl`	A Runtime Resource Management and Provisioning Middleware for Fog Computing Infrastructures. ACM Trans. Internet Things Antonio Miele, Henry Zárate, Luca Cassano, Cristiana Bolchini, Jorge Eduardo Ortiz Trivino
2022	J	`jnl`	Approximation-Based Fault Tolerance in Image Processing Applications. IEEE Trans. Emerg. Top. Comput. Matteo Biasielli, Cristiana Bolchini, Luca Cassano, Andrea Mazzeo, Antonio Miele
2022	J	`jnl`	DETON: DEfeating hardware Trojan horses in microprocessors through software ObfuscatioN. J. Syst. Archit. Luca Cassano, Mattia Iamundo, Tomas Antonio Lopez, Alessandro Nazzari, Giorgio Di Natale
2022	C	`conf`	Dependability of Alternative Computing Paradigms for Machine Learning: hype or hope? DDECS Cristiana Bolchini, Alberto Bosio, Luca Cassano, Bastien Deveautour, Giorgio Di Natale, Antonio Miele, Ian O'Connor, Elena-Ioana Vatajelu
2022	J	`jnl`	Design of Fault-Tolerant Distributed Cyber-Physical Systems for Smart Environments. IEEE Embed. Syst. Lett. Luca Cassano, Antonio Miele, Francesco Mione, Nicola Tonellotto, Carlo Vallati
2022	J	`jnl`	Fast and Accurate Error Simulation for CNNs against Soft Errors. CoRR Cristiana Bolchini, Luca Cassano, Antonio Miele, Alessandro Toschi
2022	J	`jnl`	Fault Impact Estimation for Lightweight Fault Detection in Image Filtering. IEEE Trans. Computers Cristiana Bolchini, Giacomo Boracchi, Luca Cassano, Antonio Miele, Diego Stucchi
2022	—	`ed.`	IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, DFT 2022, Austin, TX, USA, October 19-21, 2022 DFT Luca Cassano, Sreejit Chakravarty, Alberto Bosio
2022	—	`conf`	Is RISC-V ready for Space? A Security Perspective. DFT Luca Cassano, Stefano Di Mascio, Alessandro Palumbo, Alessandra Menicucci, Gianluca Furano, Giuseppe Bianchi, Marco Ottavi
2022	J	`jnl`	Is your FPGA bitstream Hardware Trojan-free? Machine learning can provide an answer. J. Syst. Archit. Alessandro Palumbo, Luca Cassano, Bruno Luzzi, José Alberto Hernández, Pedro Reviriego, Giuseppe Bianchi, Marco Ottavi
2022	C	`conf`	On the optimization of Software Obfuscation against Hardware Trojans in Microprocessors. DDECS Luca Cassano, Elia Lazzeri, Nikita Litovchenko, Giorgio Di Natale
2022	J	`jnl`	Processor Security: Detecting Microarchitectural Attacks via Count-Min Sketches. IEEE Trans. Very Large Scale Integr. Syst. Kerem Arikan, Alessandro Palumbo, Luca Cassano, Pedro Reviriego, Salvatore Pontarelli, Giuseppe Bianchi, Oguz Ergin, Marco Ottavi
2022	—	`conf`	Selective Hardening of CNNs based on Layer Vulnerability Estimation. DFT Cristiana Bolchini, Luca Cassano, Antonio Miele, Alessandro Nazzari
2021	—	`ed.`	36th IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, DFT 2021, Athens, Greece, October 6-8, 2021 DFT Luigi Dilillo, Luca Cassano, Athanasios Papadimitriou
2021	—	`conf`	A Lightweight Security Checking Module to Protect Microprocessors against Hardware Trojan Horses. DFT Alessandro Palumbo, Luca Cassano, Pedro Reviriego, Giuseppe Bianchi, Marco Ottavi
2021	J	`jnl`	On the Optimization of Behavioral Logic Locking for High-Level Synthesis. CoRR Christian Pilato, Luca Collini, Luca Cassano, Donatella Sciuto, Siddharth Garg, Ramesh Karri
2021	—	`conf`	Usability-based Cross-Layer Reliability Evaluation of Image Processing Applications. DFT Cristiana Bolchini, Luca Cassano, Andrea Mazzeo, Antonio Miele
2020	—	`conf`	A Microprocessor Protection Architecture against Hardware Trojans in Memories. DTIS Alperen Bolat, Luca Cassano, Pedro Reviriego, Oguz Ergin, Marco Ottavi
2020	J	`jnl`	A Neural Network Based Fault Management Scheme for Reliable Image Processing. IEEE Trans. Computers Matteo Biasielli, Cristiana Bolchini, Luca Cassano, Erdem Koyuncu, Antonio Miele
2020	J	`jnl`	A methodology for the design and deployment of distributed cyber-physical systems for smart environments. Future Gener. Comput. Syst. Giacomo Tanganelli, Luca Cassano, Antonio Miele, Carlo Vallati
2020	A	`conf`	An Approximation-based Fault Detection Scheme for Image Processing Applications. DATE Matteo Biasielli, Luca Cassano, Antonio Miele
2020	C	`conf`	Error Modeling for Image Processing Filters accelerated onto SRAM-based FPGAs. IOLTS Cristiana Bolchini, Luca Cassano, Andrea Mazzeo, Antonio Miele
2020	—	`conf`	Lightweight Fault Detection and Management for Image Restoration. DFT Cristiana Bolchini, Luca Cassano, Antonio Miele, Matteo Biasielli
2020	C	`conf`	Lightweight Protection of Cryptographic Hardware Accelerators against Differential Fault Analysis. IOLTS Ana Lasheras, Ramon Canal, Eva Rodríguez, Luca Cassano
2019	A	`conf`	A Smart Fault Detection Scheme for Reliable Image Processing Applications. DATE Matteo Biasielli, Cristiana Bolchini, Luca Cassano, Antonio Miele
2019	C	`conf`	HATE: a HArdware Trojan Emulation Environment for Microprocessor-based Systems. IOLTS Cristiana Bolchini, Luca Cassano, Ivan Montalbano, Giampiero Repole, Andrea Zanetti, Giorgio Di Natale
2019	—	`conf`	Protecting RSA Hardware Accelerators against Differential Fault Analysis through Residue Checking. DFT Ana Lasheras, Ramon Canal, Eva Rodríguez, Luca Cassano
2018	J	`jnl`	OLT(RE) IEEE Trans. Emerg. Top. Comput. Dario Cozzi, Sebastian Korf, Luca Cassano, Jens Hagemeyer, Andrea Domenici, Cinzia Bernardeschi, Luca Sterpone, Mario Porrmann
2017	J	`jnl`	A Fully Automated and Configurable Cost-Aware Framework for Adaptive Functional Diagnosis. IEEE Des. Test Cristiana Bolchini, Luca Cassano
2016	J	`jnl`	A Novel Approach to Incremental Functional Diagnosis for Complex Electronic Boards. IEEE Trans. Computers Cristiana Bolchini, Luca Cassano
2016	J	`jnl`	Adapting the Duty Cycle to Traffic Load in a Preamble Sampling MAC for WSNs: Formal Specification and Performance Evaluation. Ad Hoc Sens. Wirel. Networks Marco Avvenuti, Cinzia Bernardeschi, Luca Cassano, Alessio Vecchio
2016	A	`conf`	Lifetime-aware load distribution policies in multi-core systems: An in-depth analysis. DATE Cristiana Bolchini, Luca Cassano, Antonio Miele
2016	J	`jnl`	UA Integr. Cinzia Bernardeschi, Luca Cassano, Andrea Domenici, Luca Sterpone
2015	—	`conf`	A configurable board-level adaptive incremental diagnosis technique based on decision trees. DFTS Cristiana Bolchini, Luca Cassano
2015	J	`jnl`	An Expert CAD Flow for Incremental Functional Diagnosis of Complex Electronic Boards. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Cristiana Bolchini, Luca Cassano, Paolo Garza, Elisa Quintarelli, Fabio Salice
2015	J	`jnl`	SRAM-Based FPGA Systems for Safety-Critical Applications: A Survey on Design Standards and Proposed Methodologies. J. Comput. Sci. Technol. Cinzia Bernardeschi, Luca Cassano, Andrea Domenici
2014	B	`conf`	A novel adaptive fault tolerant flip-flop architecture based on TMR. ETS Luca Cassano, Alberto Bosio, Giorgio Di Natale
2014	J	`jnl`	ASSESS: A Simulator of Soft Errors in the Configuration Memory of SRAM-Based FPGAs. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Cinzia Bernardeschi, Luca Cassano, Andrea Domenici, Luca Sterpone
2014	—	`conf`	An inter-processor communication interface for data-flow centric heterogeneous embedded multiprocessor systems. DTIS Luca Cassano, Dario Cozzi, Dirk Jungewelter, Sebastian Korf, Jens Hagemeyer, Mario Porrmann, Cinzia Bernardeschi
2014	A	`conf`	Analysis and test of the effects of single event upsets affecting the configuration memory of SRAM-based FPGAs. ITC Luca Cassano
2014	J	`jnl`	Design and Safety Verification of a Distributed Charge Equalizer for Modular Li-Ion Batteries. IEEE Trans. Ind. Informatics Federico Baronti, Cinzia Bernardeschi, Luca Cassano, Andrea Domenici, Roberto Roncella, Roberto Saletti
2014	C	`conf`	Early assessment of SEU sensitivity through untestable fault identification. IOLTS Luca Cassano, Hipólito Guzmán-Miranda, Miguel A. Aguirre
2014	—	`conf`	Exploiting dynamic partial reconfiguration for on-line on-demand testing of permanent faults in reconfigurable systems. DFT Domenico G. Sorrenti, Dario Cozzi, Sebastian Korf, Luca Cassano, Jens Hagemeyer, Mario Porrmann, Cinzia Bernardeschi
2014	—	`conf`	Machine learning-based techniques for incremental functional diagnosis: A comparative analysis. DFT Cristiana Bolchini, Luca Cassano
2014	—	`conf`	Modeling and Simulation of Energy-Aware Adaptive Policies for Automatic Weather Stations. ES4CPS@DATE Daniel Cesarini, Luca Cassano, Alessio Fagioli, Marco Avvenuti
2013	—	`—`	Analysis and Test of the Effects of Single Event Upsets Affecting the Configuration Memory of SRAM-based FPGAs. Luca Cassano
2013	—	`conf`	Formal approaches to SEU testing in FPGAs. AHS Cinzia Bernardeschi, Luca Cassano, Andrea Domenici
2013	J	`jnl`	GABES: A genetic algorithm based environment for SEU testing in SRAM-FPGAs. J. Syst. Archit. Cinzia Bernardeschi, Luca Cassano, Mario G. C. A. Cimino, Andrea Domenici
2013	C	`conf`	Mitigation of Single Event Upsets in the control logic of a charge equalizer for Li-ion batteries. IECON Federico Baronti, Cinzia Bernardeschi, Luca Cassano, Andrea Domenici, Roberto Roncella, Roberto Saletti
2013	A	`conf`	On-line testing of permanent radiation effects in reconfigurable systems. DATE Luca Cassano, Dario Cozzi, Sebastian Korf, Jens Hagemeyer, Mario Porrmann, Luca Sterpone
2013	—	`conf`	Unexcitability analysis of SEus affecting the routing structure of SRAM-based FPGAs. ACM Great Lakes Symposium on VLSI Cinzia Bernardeschi, Luca Cassano, Andrea Domenici, Luca Sterpone
2012	—	`conf`	Accurate simulation of SEUs in the configuration memory of SRAM-based FPGAs. DFT Cinzia Bernardeschi, Luca Cassano, Andrea Domenici, Luca Sterpone
2012	C	`conf`	SEU-X: A SEu un-excitability prover for SRAM-FPGAs. IOLTS Cinzia Bernardeschi, Luca Cassano, Andrea Domenici
2011	B	`conf`	Failure Probability and Fault Observability of SRAM-FPGA Systems. FPL Cinzia Bernardeschi, Luca Cassano, Andrea Domenici
2011	C	`conf`	Failure probability of SRAM-FPGA systems with Stochastic Activity Networks. DDECS Cinzia Bernardeschi, Luca Cassano, Andrea Domenici