Luca Bertaccini

32 papers A 1C 5Journal 18Unranked 8
YearRankTypeTitle / Venue / Authors
2025 J jnl
A Reliable, Time-Predictable Heterogeneous SoC for AI-Enhanced Mixed-Criticality Edge Applications.
CoRR
Angelo Garofalo, Alessandro Ottaviano, Matteo Perotti, Thomas Benz, Yvan Tortorella, Robert Balas, Michael Rogenmoser, Chi Zhang, Luca Bertaccini, Nils Wistoff, Maicol Ciani, Cyril Koenig, Mattia Sinigaglia, Luca Valente, Paul Scheffler, Manuel Eggimann, Matheus A. Cavalcante, Francesco Restuccia, Alessandro Biondi, Francesco Conti, Frank K. Gürkaynak, Davide Rossi, Luca Benini
2025 J jnl
A Reliable, Time-Predictable Heterogeneous SoC for AI-Enhanced Mixed-Criticality Edge Applications.
IEEE Trans. Circuits Syst. II Express Briefs
Angelo Garofalo, Alessandro Ottaviano, Matteo Perotti, Thomas Benz, Yvan Tortorella, Robert Balas, Michael Rogenmoser, Chi Zhang, Luca Bertaccini, Nils Wistoff, Maicol Ciani, Cyril Koenig, Mattia Sinigaglia, Luca Valente, Paul Scheffler, Manuel Eggimann, Matheus A. Cavalcante, Francesco Restuccia, Alessandro Biondi, Francesco Conti, Frank K. Gürkaynak, Davide Rossi, Luca Benini
2025 — conf
MXDOTP: A RISC-V ISA Extension for Enabling Microscaling (MX) Floating-Point Dot Products.
ASAP
Gamze Islamoglu, Luca Bertaccini, Arpan Suravi Prasad, Francesco Conti, Angelo Garofalo, Luca Benini
2025 J jnl
MXDOTP: A RISC-V ISA Extension for Enabling Microscaling (MX) Floating-Point Dot Products.
CoRR
Gamze Islamoglu, Luca Bertaccini, Arpan Suravi Prasad, Francesco Conti, Angelo Garofalo, Luca Benini
2025 J jnl
Maestro: A 302 GFLOPS/W and 19.8GFLOPS RISC-V Vector-Tensor Architecture for Wearable Ultrasound Edge Computing.
CoRR
Mattia Sinigaglia, Amirhossein Kiamarzi, Marco Bertuletti, Luigi Ghionda, Mattia Orlandi, Riccardo Tedeschi, Aurora Di Giampietro, Yvan Tortorella, Luca Bertaccini, Simone Benatti, Giuseppe Tagliavini, Luca Benini, Francesco Conti, Davide Rossi
2025 J jnl
Maestro: A 302 GFLOPS/W and 19.8GFLOPS RISC-V Vector-Tensor Architecture for Wearable Ultrasound Edge Computing.
IEEE Trans. Circuits Syst. I Regul. Pap.
Mattia Sinigaglia, Amirhossein Kiamarzi, Marco Bertuletti, Luigi Ghionda, Mattia Orlandi, Riccardo Tedeschi, Aurora Di Giampietro, Yvan Tortorella, Luca Bertaccini, Simone Benatti, Giuseppe Tagliavini, Luca Benini, Francesco Conti, Davide Rossi
2025 J jnl
Occamy: A 432-Core Dual-Chiplet Dual-HBM2E 768-DP-GFLOP/s RISC-V System for 8-to-64-bit Dense and Sparse Computing in 12-nm FinFET.
IEEE J. Solid State Circuits
Paul Scheffler, Thomas Benz, Viviane Potocnik, Tim Fischer, Luca Colagrande, Nils Wistoff, Yichao Zhang, Luca Bertaccini, Gianmarco Ottavi, Manuel Eggimann, Matheus A. Cavalcante, Gianna Paulin, Frank K. Gürkaynak, Davide Rossi, Luca Benini
2025 J jnl
Occamy: A 432-Core Dual-Chiplet Dual-HBM2E 768-DP-GFLOP/s RISC-V System for 8-to-64-bit Dense and Sparse Computing in 12nm FinFET.
CoRR
Paul Scheffler, Thomas Benz, Viviane Potocnik, Tim Fischer, Luca Colagrande, Nils Wistoff, Yichao Zhang, Luca Bertaccini, Gianmarco Ottavi, Manuel Eggimann, Matheus A. Cavalcante, Gianna Paulin, Frank K. Gürkaynak, Davide Rossi, Luca Benini
2025 C conf
PACE-Lite: Compact and Efficient Piecewise Polynomial Approximation for Transformer Nonlinearity Acceleration.
ICCD
Arpan Suravi Prasad, Gamze Islamoglu, Luca Bertaccini, Davide Rossi, Francesco Conti, Luca Benini
2025 — conf
PACE: An Optimal Piecewise Polynomial Approximation Unit for Flexible and Efficient Transformer Non-linearity Acceleration.
ISVLSI
Arpan Suravi Prasad, Gamze Islamoglu, Luca Bertaccini, Davide Rossi, Francesco Conti, Luca Benini
2025 — conf
RedMulE-FT: A Reconfigurable Fault-Tolerant Matrix Multiplication Engine.
CF (Companion)
Philip Wiese, Maurus Item, Luca Bertaccini, Yvan Tortorella, Angelo Garofalo, Luca Benini
2025 J jnl
RedMulE-FT: A Reconfigurable Fault-Tolerant Matrix Multiplication Engine.
CoRR
Philip Wiese, Maurus Item, Luca Bertaccini, Yvan Tortorella, Angelo Garofalo, Luca Benini
2024 C conf
Extending RISC-V for Efficient Overflow Recovery in Mixed-Precision Computations.
ICCD
Luca Bertaccini, Siyuan Shen, Torsten Hoefler, Luca Benini
2024 J jnl
MiniFloats on RISC-V Cores: ISA Extensions With Mixed-Precision Short Dot Products.
IEEE Trans. Emerg. Top. Comput.
Luca Bertaccini, Gianna Paulin, Matheus A. Cavalcante, Tim Fischer, Stefan Mach, Luca Benini
2024 — conf
Occamy: A 432-Core 28.1 DP-GFLOP/s/W 83% FPU Utilization Dual-Chiplet, Dual-HBM2E RISC-V-Based Accelerator for Stencil and Sparse Linear Algebra Computations with 8-to-64-bit Floating-Point Support in 12nm FinFET.
VLSI Technology and Circuits
Gianna Paulin, Paul Scheffler, Thomas Benz, Matheus A. Cavalcante, Tim Fischer, Manuel Eggimann, Yichao Zhang, Nils Wistoff, Luca Bertaccini, Luca Colagrande, Gianmarco Ottavi, Frank K. Gürkaynak, Davide Rossi, Luca Benini
2024 J jnl
Occamy: A 432-Core 28.1 DP-GFLOP/s/W 83% FPU Utilization Dual-Chiplet, Dual-HBM2E RISC-V-based Accelerator for Stencil and Sparse Linear Algebra Computations with 8-to-64-bit Floating-Point Support in 12nm FinFET.
CoRR
Gianna Paulin, Paul Scheffler, Thomas Benz, Matheus A. Cavalcante, Tim Fischer, Manuel Eggimann, Yichao Zhang, Nils Wistoff, Luca Bertaccini, Luca Colagrande, Gianmarco Ottavi, Frank K. Gürkaynak, Davide Rossi, Luca Benini
2024 J jnl
Optimizing Foundation Model Inference on a Many-Tiny-Core Open-Source RISC-V Platform.
IEEE Trans. Circuits Syst. Artif. Intell.
Viviane Potocnik, Luca Colagrande, Tim Fischer, Luca Bertaccini, Daniele Jahier Pagliari, Alessio Burrello, Luca Benini
2024 J jnl
Optimizing Foundation Model Inference on a Many-tiny-core Open-source RISC-V Platform.
CoRR
Viviane Potocnik, Luca Colagrande, Tim Fischer, Luca Bertaccini, Daniele Jahier Pagliari, Alessio Burrello, Luca Benini
2023 C conf
ECHOES: a 200 GOPS/W Frequency Domain SoC with FFT Processor and I
ISCAS
Mattia Sinigaglia, Luca Bertaccini, Luca Valente, Angelo Garofalo, Simone Benatti, Luca Benini, Francesco Conti, Davide Rossi
2023 J jnl
Echoes: a 200 GOPS/W Frequency Domain SoC with FFT Processor and I2S DSP for Flexible Data Acquisition from Microphone Arrays.
CoRR
Mattia Sinigaglia, Luca Bertaccini, Luca Valente, Angelo Garofalo, Simone Benatti, Luca Benini, Francesco Conti, Davide Rossi
2023 J jnl
RedMule: A Mixed-Precision Matrix-Matrix Operation Engine for Flexible and Energy-Efficient On-Chip Linear Algebra and TinyML Training Acceleration.
CoRR
Yvan Tortorella, Luca Bertaccini, Luca Benini, Davide Rossi, Francesco Conti
2023 J jnl
RedMule: A mixed-precision matrix-matrix operation engine for flexible and energy-efficient on-chip linear algebra and TinyML training acceleration.
Future Gener. Comput. Syst.
Yvan Tortorella, Luca Bertaccini, Luca Benini, Davide Rossi, Francesco Conti
2022 C conf
MiniFloat-NN and ExSdotp: An ISA Extension and a Modular Open Hardware Unit for Low-Precision Training on RISC-V Cores.
ARITH
Luca Bertaccini, Gianna Paulin, Tim Fischer, Stefan Mach, Luca Benini
2022 J jnl
MiniFloat-NN and ExSdotp: An ISA Extension and a Modular Open Hardware Unit for Low-Precision Training on RISC-V cores.
CoRR
Luca Bertaccini, Gianna Paulin, Tim Fischer, Stefan Mach, Luca Benini
2022 A conf
RedMulE: A Compact FP16 Matrix-Multiplication Accelerator for Adaptive Deep Learning on RISC-V-Based Ultra-Low-Power SoCs.
DATE
Yvan Tortorella, Luca Bertaccini, Davide Rossi, Luca Benini, Francesco Conti
2022 J jnl
RedMulE: A Compact FP16 Matrix-Multiplication Accelerator for Adaptive Deep Learning on RISC-V-Based Ultra-Low-Power SoCs.
CoRR
Yvan Tortorella, Luca Bertaccini, Davide Rossi, Luca Benini, Francesco Conti
2022 — conf
Soft Tiles: Capturing Physical Implementation Flexibility for Tightly-Coupled Parallel Processing Clusters.
ISVLSI
Gianna Paulin, Matheus A. Cavalcante, Paul Scheffler, Luca Bertaccini, Yichao Zhang, Frank K. Gürkaynak, Luca Benini
2022 J jnl
Soft Tiles: Capturing Physical Implementation Flexibility for Tightly-Coupled Parallel Processing Clusters.
CoRR
Gianna Paulin, Matheus A. Cavalcante, Paul Scheffler, Luca Bertaccini, Yichao Zhang, Frank K. Gürkaynak, Luca Benini
2021 — conf
A 10-core SoC with 20 Fine-Grain Power Domains for Energy-Proportional Data-Parallel Processing over a Wide Voltage and Temperature Range.
ESSCIRC
Thomas Benz, Luca Bertaccini, Florian Zaruba, Fabian Schuiki, Frank K. Gürkaynak, Luca Benini
2021 — conf
RVfplib: A Fast and Compact Open-Source Floating-Point Emulation Library for Tiny RISC-V Processors.
SAMOS
Matteo Perotti, Giuseppe Tagliavini, Stefan Mach, Luca Bertaccini, Luca Benini
2021 C conf
Tiny-FPU: Low-Cost Floating-Point Support for Small RISC-V MCU Cores.
ISCAS
Luca Bertaccini, Matteo Perotti, Stefan Mach, Pasquale Davide Schiavone, Florian Zaruba, Luca Benini
2021 — conf
To Buffer, or Not to Buffer? A Case Study on FFT Accelerators for Ultra-Low-Power Multicore Clusters.
ASAP
Luca Bertaccini, Luca Benini, Francesco Conti