Luc Rijnders

13 papers A* 2A 1B 1C 2Journal 3Unranked 4
YearRankTypeTitle / Venue / Authors
2016 — conf
Towards high performance sub-10nm finW bulk FinFET technology.
ESSDERC
Thomas Chiarella, Stefan Kubicek, E. Rosseel, Romain Ritzenthaler, Andriy Hikavyy, P. Eyben, An De Keersgieter, L.-Å. Ragnarsson, M.-S. Kim, S.-A. Chew, Tom Schram, S. Demuynck, Miroslav Cupák, Luc Rijnders, Morin Dehan, Naoto Horiguchi, Jérôme Mitard, Dan Mocuta, Anda Mocuta, Aaron Voon-Yew Thean
2006 B conf
System Level Architecture Exploration for Reconfigurable Systems On Chip.
FPL
Konstantinos Masselos, Kari Tiensyrjä, Yang Qu, Nikolaos S. Voros, Miroslav Cupák, Luc Rijnders, Marko Pettissalo
2003 C conf
Performance Analysis for Identification of (Sub-)Task-Level Parallelism in Java.
SCOPES
Richard Stahl, Robert Pasko, Luc Rijnders, Diederik Verkest, Serge Vernalde, Rudy Lauwereins, Francky Catthoor
2001 J jnl
High-performance flexible all-digital quadrature up and down converter chip.
IEEE J. Solid State Circuits
Robert Pasko, Luc Rijnders, Patrick R. Schaumont, Serge A. Vernalde, Daniela Duracková
2000 C conf
A Hardware Virtual Machine for the Networked Reconfiguration.
IEEE International Workshop on Rapid System Prototyping
Yajun Ha, Patrick Schaumont, Marc Engels, Serge Vernalde, Freddy Potargent, Luc Rijnders, Hugo De Man
2000 — conf
High-performance flexible all-digital quadrature up and down converter chip.
CICC
Robert Pasko, Luc Rijnders, Patrick Schaumont, Serge Vernalde, Daniela Duracková
1999 A conf
A Methodology and Design Environment for DSP ASIC Fixed-Point Refinement.
DATE
Radim Cmar, Luc Rijnders, Patrick Schaumont, Serge Vernalde, Ivo Bolsens
1998 A* conf
A Programming Environment for the Design of Complex High Speed ASICs.
DAC
Patrick Schaumont, Serge Vernalde, Luc Rijnders, Marc Engels, Ivo Bolsens
1997 — conf
Synthesis of multi-rate and variable rate circuits for high speed telecommunications applications.
ED&TC
Patrick Schaumont, Serge Vernalde, Luc Rijnders, Marc Engels, Ivo Bolsens
1995 — conf
Timing optimization by bit-level arithmetic transformations.
EURO-DAC
Luc Rijnders, Zohair Sahraoui, Paul Six, Hugo De Man
1989 A* conf
REDUSA: Module Generation by Automatic Elimination of Superfluous Blocks in Regular Structures.
DAC
I. Vandeweerd, Kris Croes, Luc Rijnders, Paul Six, Hugo De Man
1989 J jnl
REDUSA: module generation by automatic elimination of superfluous blocks in regular structures.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
I. Vandeweerd, Kris Croes, Luc Rijnders, Paul Six, Hugo De Man
1988 J jnl
Design of a process-tolerant cell library for regular structures using symbolic layout and hierarchical compaction.
IEEE J. Solid State Circuits
Luc Rijnders, Paul Six, Hugo J. De Man