Luc J. M. Claesen

45 papers A* 4A 3B 1C 6Misc 1Journal 9Unranked 19

Year	Rank	Type	Title / Venue / Authors
1999	A	`conf`	Formally Verified Redundancy Removal. DATE Stefan Hendricx, Luc J. M. Claesen
1999	—	`conf`	Symbolic Multi-Level Verification of Refinement. Great Lakes Symposium on VLSI Stefan Hendricx, Luc J. M. Claesen
1999	—	`conf`	Verification of Finite-State-Machine Refinements Using a Symbolic Methodology. CHARME Stefan Hendricx, Luc J. M. Claesen
1998	J	`jnl`	Incorporating local consistency information into the online signature verification process. Int. J. Document Anal. Recognit. Ronny Martens, Luc J. M. Claesen
1997	—	`conf`	A symbolic core approach to the formal verification of integrated mixed-mode applications. ED&TC Stefan Hendricx, Luc J. M. Claesen
1997	—	`conf`	An Evaluation of Different Handwriting Observation Techniques from a Signature Verification Point of View. BSDIA Ronny Martens, Luc J. M. Claesen
1997	A	`conf`	Dynamic Programming Optimisation for On-line Signature Verificatio. ICDAR Ronny Martens, Luc J. M. Claesen
1997	A	`conf`	On-line Signature Verification: Discrimination Emphasised. ICDAR Ronny Martens, Luc J. M. Claesen
1996	C	`conf`	A formal verification technique for embedded software. ICCD Olivier Thiry, Luc J. M. Claesen
1996	B	`conf`	On-line signature verification by dynamic time-warping. ICPR Ronny Martens, Luc J. M. Claesen
1995	J	`jnl`	ED&TC 1995: Simulation versus formal verification. IEEE Des. Test Comput. Luc J. M. Claesen
1994	C	`conf`	A Parallel Method for Functional Verification of Medium and High Throughput DSP Synthesis. ICCD Mark Genoe, Luc J. M. Claesen, Hugo De Man
1994	J	`jnl`	A Proof of the Nonrestoring Division Algorithm and its Implementation on an ALU. Formal Methods Syst. Des. Diederik Verkest, Luc J. M. Claesen, Hugo De Man
1994	J	`jnl`	Modeling Multi-rate DSP Specification Semantics for Formal Transformational Design in HOL. Formal Methods Syst. Des. Catia M. Angelo, Luc J. M. Claesen, Hugo De Man
1994	—	`conf`	Reasoning About a Class of Linear Systems of Equations in HOL. TPHOLs Catia M. Angelo, Luc J. M. Claesen, Hugo De Man
1993	—	`conf`	An Architecture for Ray - Bezier Patch Intersection. Workshop on Graphics Hardware Peter De Vijt, Luc J. M. Claesen, Hugo De Man
1993	—	`ed.`	Computer Hardware Description Languages and their Applications, Proceedings of the 11th IFIP WG10.2 International Conference on Computer Hardware Description Languages and their Applications - CHDL '93, sponsored by IFIP WG10.2 and in cooperation with IEEE COMPSOC, Ottawa, Ontario, Canada, 26-28 April, 1993 CHDL David Agnew, Luc J. M. Claesen, Raul Camposano
1993	—	`conf`	Degrees of Formality in Shallow Embedding Hardware Description Languages in HOL. HUG Catia M. Angelo, Luc J. M. Claesen, Hugo De Man
1993	—	`ed.`	Higher Order Logic Theorem Proving and its Applications, Proceedings of the IFIP TC10/WG10.2 Workshop HOL'92, Leuven, Belgium, 21-24 September 1992 TPHOLs Luc J. M. Claesen, Michael J. C. Gordon
1993	J	`jnl`	On the Comparison of HOL and Boyer-Moore for Formal Hardware Verification. Formal Methods Syst. Des. Catia M. Angelo, Diederik Verkest, Luc J. M. Claesen, Hugo De Man
1993	C	`conf`	Subterranean: A 600 Mbit/Sec Cryptographic VLSI Chip. ICCD Luc J. M. Claesen, Joan Daemen, Mark Genoe, G. Peeters
1992	—	`conf`	A Description Methodology for Parameterized Modules in the Boyer-Moore Logic. TPCD Diederik Verkest, J. Vandenbergh, Luc J. M. Claesen, Hugo De Man
1992	—	`conf`	A Proof of the Non-Restoring Division Algorithm and its Implementation on the Cathedral-II ALU. Designing Correct Circuits Diederik Verkest, Luc J. M. Claesen, Hugo De Man
1992	—	`conf`	ASICs for a High Performance IVIulti Processor Systemfor Photo-realistic Image Synthesis. Eurographics Workshop on Graphics Hardware Peter De Vijt, Luc J. M. Claesen, Hugo De Man
1992	—	`conf`	On the use of hierarchy in timing verification with statically sensitizable paths. Great Lakes Symposium on VLSI P. Johannes, Luc J. M. Claesen, Hugo De Man
1992	—	`conf`	Performance Through Hierarchy in Static Timing Verification. IFIP Congress (1) P. Johannes, Luc J. M. Claesen, Hugo De Man
1992	—	`conf`	The Formal Semantics Definition of a Multi-Rate DSP Specification Language in HOL. TPHOLs Catia M. Angelo, Luc J. M. Claesen, Hugo De Man
1991	—	`conf`	Defining Recursive Functions in HOL. TPHOLs W. Ploegaerts, Luc J. M. Claesen, Hugo De Man
1991	—	`conf`	Formal Hardware Verification in HOL and in Boyer-Moore: A Comparative Analysis. TPHOLs Catia M. Angelo, Diederik Verkest, Luc J. M. Claesen, Hugo De Man
1991	C	`conf`	Illustration of the SFG-Tracing Multi-Level Behavioral Verification Methodology, by the Correctness Proof of a High to Low Level Synthesis Application in CATHEDRAL-II. ICCD Mark Genoe, Luc J. M. Claesen, Eric Verlind, Frank Proesmans, Hugo De Man
1990	—	`conf`	A combined waveform relaxation: waveform relaxation newton algorithm for efficient parallel circuit simulation. EURO-DAC Patrick Odent, Luc J. M. Claesen, Hugo De Man
1990	J	`jnl`	Acceleration of relaxation-based circuit simulation using a multiprocessor system. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Patrick Odent, Luc J. M. Claesen, Hugo De Man
1990	—	`conf`	Correctness proofs of parameterized hardware modules in the CATHEDRAL-II synthesis environment. EURO-DAC Diederik Verkest, Luc J. M. Claesen, Hugo De Man
1990	C	`conf`	Derivation of signal flow direction in MOS VLSI: an alternative. ICCD W. De Rammelaere, Ivo Bolsens, Luc J. M. Claesen, Hugo De Man
1990	—	`conf`	SLOCOP-II: a versatile timing verification system for MOSVLSI. EURO-DAC P. Johannes, P. Das, Luc J. M. Claesen, Hugo De Man
1990	—	`conf`	SPI: an open interface integrating highly interactive electronic CAD tools. EURO-DAC J. P. Schupp, Johan Cockx, Luc J. M. Claesen, Hugo De Man
1990	J	`jnl`	Timing verification using statically sensitizable paths. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Jacques Benkoski, E. Vanden Meersch, Luc J. M. Claesen, Hugo De Man
1989	C	`conf`	Correctness verification of VLSI modules supported by a very efficient Boolean prover. ICCD P. Lammens, Luc J. M. Claesen, Hugo De Man
1989	J	`jnl`	Efficient false path elimination algorithms for timing verification by event graph preprocessing. Integr. Luc J. M. Claesen, J. P. Schupp, P. Das, P. Johannes, S. Perremans, Hugo De Man
1989	A*	`conf`	Electrical Debugging of Synchronous MOS VLSI Circuits Exploiting Analysis of the Intended Logic Behaviour. DAC Ivo Bolsens, W. De Rammelaere, Luc J. M. Claesen, Hugo De Man
1989	A*	`conf`	Feedback Loops and Large Subcircuits in the Multiprocessor Implementation of a Relaxation Based Circuit Simulator. DAC Patrick Odent, Luc J. M. Claesen, Hugo De Man
1989	A*	`conf`	Static Timing Analysis of Dynamically Sensitizable Paths. DAC S. Perremans, Luc J. M. Claesen, Hugo De Man
1986	A*	`conf`	An intelligent module generator environment. DAC Paul Six, Luc J. M. Claesen, Jan M. Rabaey, Hugo De Man
1986	J	`jnl`	Cathedral-II: A Silicon Compiler for Digital Signal Processing. IEEE Des. Test Hugo De Man, Jan M. Rabaey, Paul Six, Luc J. M. Claesen
1985	Misc	`conf`	CAD Tools for the optimized design of custom VLSI wave digital filters. ICASSP Rajeev Jain, Gert Goossens, Luc J. M. Claesen, Joos Vandewalle, Hugo De Man, L. Gazsi, Alfred Fettweis