Lu Jie - RankMe

54 papers A* 1C 6Journal 17Unranked 30

Year	Rank	Type	Title / Venue / Authors
2026	—	`conf`	11.1 A 14b 400MS/s TDC-Assisted Pipelined-SAR ADC with Rail-to-Rail Input VTC and Background Time-Domain Error Calibration. ISSCC Jingpeng Wang, Bingrui Li, Haoyang Luo, Mingtao Zhan, Xiyu He, Dawei Shen, Lu Jie, Xiyuan Tang
2026	—	`conf`	21.8 A CMOS Hybrid Common-Gate Current-Integrating Sampler with <37dB SNDR Across 51GHz BW in a 128GS/s Front-End. ISSCC Jun Dai, Yi Zhong, Yunsong Tao, Aodong Zhang, Mingtao Zhan, Hao Zhang, Lu Jie, Nan Sun
2026	—	`conf`	A 13b 500MS/s 94dB-SFDR Resistive-Input Pipelined-SAR ADC with Linear and Efficient Current-Buffer-Based Integrating Sampler. ISSCC Xiyu He, Mingyang Gu, Yunsong Tao, Siyu Huang, Zhishuai Zhang, Yi Zhong, Nan Sun, Lu Jie
2026	—	`conf`	A 98.5dB-SNDR 250kHz-BW 1V-Supply Continuous-Time Zoom ADC with Smart-Tracking and Floating-Tail-Resistor Linearized Gm-C Loop Filter. ISSCC Chaoyang Xing, Yilu Cui, Sining Pan, Yi Zhong, Nan Sun, Lu Jie
2026	A*	`conf`	AMS-IO-Bench and AMS-IO-Agent: Benchmarking and Structured Reasoning for Analog and Mixed-Signal Integrated Circuit Input/Output Design. AAAI Zhishuai Zhang, Xintian Li, Shilong Liu, Aodong Zhang, Lu Jie, Nan Sun
2026	J	`jnl`	An Easy-Driving Incremental Zoom ADC With Skipped Sampling Scheme and NS-SAR Quantizer. IEEE J. Solid State Circuits Zongnan Wang, Lu Jie, Zichen Kong, Mingtao Zhan, Yi Zhong, Yuan Wang, Xiyuan Tang
2025	—	`conf`	24.1 A 12b 3GS/s Pipelined ADC with Gated-LMS-Based Piecewise-Linear Nonlinearity Calibration. ISSCC Mingyang Gu, Yi Zhong, Lu Jie, Nan Sun
2025	—	`conf`	3.4: A CMOS Operational Amplifier Achieving ±5.8µV 3σ Offset and ±88nV/°C 3σ Offset Drift Using an on-Chip Heater-Based Self-Trimming Technique. ISSCC Aodong Zhang, Mingtao Zhan, Mengying Chen, Yi Zhong, Lu Jie, Nan Sun, Qinwen Fan
2025	—	`conf`	A 0.16mm CICC Heyang Zhao, Yuxuan He, Yunsong Tao, Zhishuai Zhang, Yong Chen, Yi Zhong, Lu Jie, Nan Sun
2025	J	`jnl`	A 1-GS/s 11-b Time-Interleaved SAR ADC With Robust, Fast, and Accurate Autocorrelation-Based Background Timing-Skew Calibration. IEEE J. Solid State Circuits Mingyang Gu, Yunsong Tao, Xiyu He, Yi Zhong, Lu Jie, Nan Sun
2025	J	`jnl`	A 28-nm Static-Power-Free Fully Parallel RRAM-Based TD CIM Macro With 1982 TOPS/W/Bit for Edge Applications. IEEE Solid State Circuits Lett. Songtao Wei, Peng Yao, Xinying Guo, Dong Wu, Lu Jie, Qi Qin, Bin Gao, Jianshi Tang, He Qian, Sining Pan, Huaqiang Wu
2025	—	`conf`	A 70dB SNDR 80MHz BW Filter-Embedded Pipeline-SAR ADC Achieving 172dB FoMs with Progressive Conversion and Floating-Charge-Transfer Amplifier. ISSCC Siyu Huang, Zhishuai Zhang, Xiyu He, Mingyang Gu, Yunsong Tao, Yi Zhong, Nan Sun, Lu Jie
2025	C	`conf`	A 75-MHz-BW 3rd-order Time-Interleaved Noise-Shaping SAR ADC with Shared EF-CIFF Loop Filter and Ring Buffer. ISCAS Xiyu He, Yi Zhong, Nan Sun, Lu Jie
2025	J	`jnl`	A Filter-Embedded Pipe-SAR ADC With Progressive Conversion and Floating Charge Transfer Amplifier. IEEE J. Solid State Circuits Siyu Huang, Zhishuai Zhang, Xiyu He, Lu Jie
2025	C	`conf`	A Hierarchical Compilation Method for Programmable Analog-to-Digital Converter Arrays. ISCAS Zhishuai Zhang, Siyu Huang, Yi Zhong, Nan Sun, Lu Jie
2025	—	`conf`	A Power-Efficient Jitter-Insensitive 3.2GHz 1-bit CT ΔΣ ADC with Direct Charge Dump Feedback. CICC Yanquan Luo, Lu Jie, Nan Sun
2025	J	`jnl`	A RRAM-Based CIM Design With in-Situ Transposable Computing and Hybrid-Precision Scheme for Edge Learning. IEEE Solid State Circuits Lett. Qiumeng Wei, Peng Yao, Dong Wu, Qi Qin, Bin Gao, Qingtian Zhang, Sining Pan, Jianshi Tang, He Qian, Lu Jie, Huaqiang Wu
2025	J	`jnl`	AMS-IO-Bench and AMS-IO-Agent: Benchmarking and Structured Reasoning for Analog and Mixed-Signal Integrated Circuit Input/Output Design. CoRR Zhishuai Zhang, Xintian Li, Shilong Liu, Aodong Zhang, Lu Jie, Nan Sun
2025	J	`jnl`	An 8-bit 20.7 TOPS/W Multilevel Cell ReRAM Macro With ADC-Assisted Bit-Serial Processing. IEEE J. Solid State Circuits Justin M. Correll, Lu Jie, Seungheun Song, Seungjong Lee, Junkang Zhu, Wei Tang, Luke Wormald, Jack Erhardt, Nicolas Breil, Roger Quon, Deepak Kamalanathan, Siddarth A. Krishnan, Michael Chudzik, Wei D. Lu, Zhengya Zhang, Michael P. Flynn
2025	—	`conf`	An 8b 10GS/s 2-Channel Time-Interleaved Pipelined ADC with Concurrent Residue Transfer and Quantization, and Automatic Buffer Power Gating. ISSCC Yunsong Tao, Mingtao Zhan, Mingyang Gu, Xiyu He, Yuxuan He, Zhishuai Zhang, Yi Zhong, Lu Jie, Nan Sun
2025	J	`jnl`	First-In-Last-Out Data Weighted Averaging Technique for Multi-Bit ΔΣ ADCs. IEEE Trans. Circuits Syst. II Express Briefs Xing Wang, Chaoyang Xing, Yi Zhong, Lu Jie, Nan Sun
2025	C	`conf`	Live Demonstration: A Programmable A/D Converter Array with Interactive Compiler. ISCAS Zhishuai Zhang, Chitian Yuan, Jiantao Li, Kun Lin, Yi Zhong, Nan Sun, Lu Jie
2025	J	`jnl`	Programmable Analog-to-Digital Converter Array Supporting Architecture Restructuring and Mode Concurrency. IEEE Trans. Circuits Syst. I Regul. Pap. Zhishuai Zhang, Mingtao Zhan, Zijie Gao, Siyu Huang, Mingyang Gu, Yunsong Tao, Xiyu He, Chitian Yuan, Yi Zhong, Nan Sun, Lu Jie
2024	—	`conf`	22.4 A 4.8GS/s 7-ENoB Time-Interleaved SAR ADC with Dither-Based Background Timing-Skew Calibration and Bit-Distribution-Based Background Ping-Pong Comparator Offset Calibration. ISSCC Yunsong Tao, Mingyang Gu, Baoyong Chi, Yi Zhong, Lu Jie, Nan Sun
2024	—	`conf`	9.3 A 71dB SNDR 200MHz BW Interleaved Pipe-SAR ADC with a Shared Residue Integrating Amplifier Achieving 173dB FoMs. ISSCC Xiyu He, Mingyang Gu, Hanjun Jiang, Yi Zhong, Nan Sun, Lu Jie
2024	J	`jnl`	A 0.004-mm IEEE J. Solid State Circuits Mingtao Zhan, Lu Jie, Xiyuan Tang, Yi Zhong, Nan Sun
2024	—	`conf`	A 1.2GS/s 11b Time-Interleaved SAR ADC with Low-Cost Derivative-Based Background Timing-Skew Calibration and Variable-Load Comparators. A-SSCC Mingyang Gu, Yunsong Tao, Xiyu He, Yi Zhong, Lu Jie, Nan Sun
2024	—	`conf`	A 92.9dB-SNDR 178.2dB-FoMs SAR ADC with kT/C noise cancellation and FIA. ICTA Zijie Gao, Yi Zhong, Lu Jie, Nan Sun
2024	C	`conf`	A Dithered-Digital-Mixing Background Timing-Skew Calibration Method for Time-Interleaved ADCs. ISCAS Yunsong Tao, Yi Zhong, Jin Shao, Changyou Men, Lu Jie, Nan Sun
2023	—	`conf`	A 0.021mm ESSCIRC Chaoyang Xing, Yi Zhong, Nan Sun, Lu Jie
2023	J	`jnl`	A 10-mW 10-ENoB 1-GS/s Ring-Amp-Based Pipelined TI-SAR ADC With Split MDAC and Switched Reference Decoupling Capacitor. IEEE J. Solid State Circuits Mingtao Zhan, Lu Jie, Yi Zhong, Nan Sun
2023	—	`conf`	A 10mW 10-ENOB 1GS/s Ring-Amp-Based Pipelined TI-SAR ADC with Split MDAC and Switched Reference Decoupling Capacitor. ISSCC Mingtao Zhan, Lu Jie, Nan Sun
2023	—	`conf`	A 12b 1GS/s Pipelined ADC with Digital Background Calibration of Inter-stage Gain, Capacitor Mismatch, and Kick-back Errors. ESSCIRC Mingyang Gu, Yi Zhong, Lu Jie, Nan Sun
2023	—	`conf`	A 150kHz-BW 15-ENOB Incremental Zoom ADC with Skipped Sampling and Single Buffer Embedded Noise-Shaping SAR Quantizer. ISSCC Zongnan Wang, Lu Jie, Zichen Kong, Mingtao Zhan, Yi Zhong, Yuan Wang, Xiyuan Tang
2023	—	`conf`	A 1GS/s6-Core Programmable A/D Converter Array Supporting Architecture Restructuring and Multitasking. CICC Zhishuai Zhang, Zijie Gao, Siyu Huang, Nan Sun, Lu Jie
2023	—	`conf`	A 3.7mW 11b 1GS/s Time-Interleaved SAR ADC with Robust One-Stage Correlation-Based Background Timing-Skew Calibration. ESSCIRC Mingyang Gu, Yunsong Tao, Xiyu He, Yi Zhong, Lu Jie, Nan Sun
2023	—	`conf`	A 5.6-89.9TOPS/W Heterogeneous Computing-in-Memory SoC with High-Utilization Producer-Consumer Architecture and High-Frequency Read-Free CIM Macro. VLSI Technology and Circuits Jinshan Yue, Mingtao Zhan, Zi Wang, Yifan He, Yaolei Li, Songming Yu, Wenyu Sun, Lu Jie, Chunmeng Dou, Xueqing Li, Nan Sun, Huazhong Yang, Ming Liu, Yongpan Liu
2023	—	`conf`	An 80.2-to-89.1dB-SNDR 24k-to-200kHz-BW VCO-Based Synthesized ?S ADC with 105dB SFDR in 28-nm CMOS. CICC Yi Zhong, Mingtao Zhan, Wei Wang, Xiyuan Tang, Lu Jie, Nan Sun
2022	—	`conf`	A 0.004mm ISSCC Mingtao Zhan, Lu Jie, Xiyuan Tang, Nan Sun
2022	—	`conf`	A 0.014mm ISSCC Lu Jie, Mingtao Zhan, Xiyuan Tang, Nan Sun
2022	—	`conf`	A 0.37mm CICC Wei Shi, Xing Wang, Xiyuan Tang, Abhishek Mukherjee, Raviteja Theertham, Shanthi Pavan, Lu Jie, Nan Sun
2022	C	`conf`	A Fast Converging Correlation-Based Background Timing Skew Calibration Technique by Digital Windowing for Time-Interleaved ADCs. ISCAS Yunsong Tao, Kareem Ragab, Jin Shao, Pengpeng Chen, Yi Zhong, Lu Jie, Nan Sun
2022	C	`conf`	A Second-Order VCO-Based ΔΣ ADC with Fully Digital Feedback Summation. ISCAS Chaoyang Xing, Yi Zhong, Jin Shao, Pengpeng Chen, Lu Jie, Nan Sun
2022	—	`conf`	An 8-bit 20.7 TOPS/W Multi-Level Cell ReRAM-based Compute Engine. VLSI Technology and Circuits Justin M. Correll, Lu Jie, Seungheun Song, Seungjong Lee, Junkang Zhu, Wei Tang, Luke Wormald, Jack Erhardt, Nicolas Breil, Roger Quon, Deepak Kamalanathan, Siddarth A. Krishnan, Michael Chudzik, Zhengya Zhang, Wei D. Lu, Michael P. Flynn
2021	—	`conf`	10.3 A 100MHz-BW 68dB-SNDR Tuning-Free Hybrid-Loop DSM with an Interleaved Bandpass Noise-Shaping SAR Quantizer. ISSCC Lu Jie, Hsiang-Wen Chen, Boyi Zheng, Michael P. Flynn
2021	J	`jnl`	A Hybrid-Loop Structure and Interleaved Noise-Shaped Quantizer for a Robust 100-MHz BW and 69-dB DR DSM. IEEE J. Solid State Circuits Lu Jie, Hsiang-Wen Chen, Boyi Zheng, Michael P. Flynn
2021	—	`conf`	TaNS-DDRF: A 160-MHz Bandwidth 6-GHz Carrier Frequency Digital-Direct RF Transmitter for Wi-Fi 6E with Targeted Noise-Shaping. ESSCIRC Boyi Zheng, Lu Jie, Michael P. Flynn
2020	—	`conf`	9.4 A 4 ISSCC Lu Jie, Boyi Zheng, Hsiang-Wen Chen, Runyu Wang, Michael P. Flynn
2020	J	`jnl`	A Cascaded Noise-Shaping SAR Architecture for Robust Order Extension. IEEE J. Solid State Circuits Lu Jie, Boyi Zheng, Hsiang-Wen Chen, Michael P. Flynn
2019	—	`conf`	A 50MHz-Bandwidth 70.4dB-SNDR Calibration-Free Time-Interleaved 4 ISSCC Lu Jie, Boyi Zheng, Michael P. Flynn
2019	J	`jnl`	A Calibration-Free Time-Interleaved Fourth-Order Noise-Shaping SAR ADC. IEEE J. Solid State Circuits Lu Jie, Boyi Zheng, Michael P. Flynn
2019	J	`jnl`	Design Considerations for Integrated Radar Chirp Synthesizers. IEEE Access Daniel Weyer, Mehmet Batuhan Dayanik, Lu Jie, Ahmed Albalawi, Abdulhamed Alothaimen, Mohammed Aseeri, Michael P. Flynn
2018	J	`jnl`	A Mismatch-Immune 12-Bit SAR ADC With Completely Reconfigurable Capacitor DAC. IEEE Trans. Circuits Syst. II Express Briefs Nicholas Collins, Andres Tamez, Lu Jie, Jorge Pernillo, Michael P. Flynn
2017	J	`jnl`	A low power V-band LC VCO with high Q varactor technique in 40 nm CMOS process. Sci. China Inf. Sci. Qian Zhou, Yan Han, Shifeng Zhang, Xiaoxia Han, Lu Jie, Ray C. C. Cheung, Guangtao Feng