Loïs Guiller - RankMe

17 papers A 4Misc 2Journal 3Unranked 8

Year	Rank	Type	Title / Venue / Authors
2006	J	`jnl`	A Gated Clock Scheme for Low Power Testing of Logic Cores. J. Electron. Test. Yannick Bonhomme, Patrick Girard, Loïs Guiller, Christian Landrault, Serge Pravossoudovitch, Arnaud Virazel
2004	A	`conf`	Design of Routing-Constrained Low Power Scan Chains. DATE Yannick Bonhomme, Patrick Girard, Loïs Guiller, Christian Landrault, Serge Pravossoudovitch, Arnaud Virazel
2004	—	`conf`	Design of Routing-Constrained Low Power Scan Chains. DELTA Yannick Bonhomme, Patrick Girard, Loïs Guiller, Christian Landrault, Serge Pravossoudovitch, Arnaud Virazel
2004	J	`jnl`	Power-Driven Routing-Constrained Scan Chain Design. J. Electron. Test. Yannick Bonhomme, Patrick Girard, Loïs Guiller, Christian Landrault, Serge Pravossoudovitch
2003	A	`conf`	Efficient Scan Chain Design for Power Minimization During Scan Testing Under Routing Constraint. ITC Yannick Bonhomme, Patrick Girard, Loïs Guiller, Christian Landrault, Serge Pravossoudovitch
2002	A	`conf`	Integrating DFT in the Physical Synthesis Flow. ITC Loïs Guiller, Frederic Neuveux, S. Duggirala, R. Chandramouli, Rohit Kapur
2001	—	`conf`	A Gated Clock Scheme for Low Power Scan Testing of Logic ICs or Embedded Cores. Asian Test Symposium Yannick Bonhomme, Patrick Girard, Loïs Guiller, Christian Landrault, Serge Pravossoudovitch
2001	—	`conf`	A Gated Clock Scheme for Low Power Scan-Based BIST. IOLTW Yannick Bonhomme, Patrick Girard, Loïs Guiller, Christian Landrault, Serge Pravossoudovitch
2001	Misc	`conf`	A Modified Clock Scheme for a Low Power BIST Test Pattern Generator. VTS Patrick Girard, Loïs Guiller, Christian Landrault, Serge Pravossoudovitch, Hans-Joachim Wunderlich
2000	—	`conf`	An adjacency-based test pattern generator for low power BIST design. Asian Test Symposium Patrick Girard, Loïs Guiller, Christian Landrault, Serge Pravossoudovitch
2000	J	`jnl`	Low Power BIST by Filtering Non-Detecting Vectors. J. Electron. Test. Salvador Manich, A. Gabarró, M. Lopez, Joan Figueras, Patrick Girard, Loïs Guiller, Christian Landrault, Serge Pravossoudovitch, João Paulo Teixeira, Marcelino B. Santos
2000	A	`conf`	Low power BIST design by hypergraph partitioning: methodology and architectures. ITC Patrick Girard, Christian Landrault, Loïs Guiller, Serge Pravossoudovitch
1999	Misc	`conf`	A Test Vector Inhibiting Technique for Low Energy BIST Design. VTS Patrick Girard, Loïs Guiller, Christian Landrault, Serge Pravossoudovitch
1999	—	`conf`	A Test Vector Ordering Technique for Switching Activity Reduction During Test Operation. Great Lakes Symposium on VLSI Patrick Girard, Loïs Guiller, Christian Landrault, Serge Pravossoudovitch
1999	—	`conf`	Circuit Partitioning for Low Power BIST Design with Minimized Peak Power Consumption. Asian Test Symposium Patrick Girard, Loïs Guiller, Christian Landrault, Serge Pravossoudovitch
1999	—	`conf`	Low power BIST by filtering non-detecting vectors. ETW Salvador Manich, A. Gabarró, M. Lopez, Joan Figueras, Patrick Girard, Loïs Guiller, Christian Landrault, Serge Pravossoudovitch, João Paulo Teixeira, Marcelino B. Santos
1999	—	`conf`	Low-energy BIST design: impact of the LFSR TPG parameters on the weighted switching activity. ISCAS (1) Patrick Girard, Loïs Guiller, Christian Landrault, Serge Pravossoudovitch, Joan Figueras, Salvador Manich, João Paulo Teixeira, Marcelino B. Santos