Lounis Kessal

24 papers B 5C 4Journal 8Unranked 7
YearRankTypeTitle / Venue / Authors
2023 J jnl
Implementation of a Bio-Inspired Neural Architecture for Autonomous Vehicles on a Multi-FPGA Platform.
Sensors
Tarek Elouaret, Sylvain Colomer, Frédéric de Melo, Nicolas Cuperlier, Olivier Romain, Lounis Kessal, Stéphane Zuckerman
2022 — conf
Implementation of a bio-inspired neural architecture for autonomous vehicle on a reconfigurable platform.
ISIE
Tarek Elouaret, Sylvain Colomer, Frédéric Demelo, Nicolas Cuperlier, Olivier Romain, Lounis Kessal, Stéphane Zuckerman
2019 J jnl
A Probabilistic Parallel Bit-Flipping Decoder for Low-Density Parity-Check Codes.
IEEE Trans. Circuits Syst. I Regul. Pap.
Khoa Le, Fakhreddine Ghaffari, Lounis Kessal, David Declercq, Emmanuel Boutillon, Chris Winstead, Bane Vasic
2019 — conf
Position Paper: Prototyping Autonomous Vehicles Applications with Heterogeneous Multi-FpgaSystems.
UCET
Tarek Elouaret, Stéphane Zuckerman, Lounis Kessal, Yoan Espada, Nicolas Cuperlier, Guillaume Bresson, Fethi Ben Ouezdou, Olivier Romain
2018 C conf
Lightweight Hardware Architecture for Probabilistic Gradient Descent Bit Flipping on QC-LDPC Codes.
ISCAS
Khoa Le, Fakhreddine Ghaffari, Lounis Kessal, David Declercq, Valentin Savin, Oana Boncalo
2018 J jnl
Variable-Node-Shift Based Architecture for Probabilistic Gradient Descent Bit Flipping on QC-LDPC Codes.
IEEE Trans. Circuits Syst. I Regul. Pap.
Khoa Le, David Declercq, Fakhreddine Ghaffari, Lounis Kessal, Oana Boncalo, Valentin Savin
2017 B conf
Density evolution thresholds for noise-against-noise min-sum decoders.
PIMRC
Franklin Cochachin, David Declercq, Emmanuel Boutillon, Lounis Kessal
2014 — conf
FPGA-implementation of a bio-inspired medical hearing aid based DWT-OLA.
ICAILP
Lotfi Bendaouia, Hassen Salhi, Si Mahmoud Karabernou, Lounis Kessal, Fayçal Ykhlef
2012 J jnl
Enhancing Reconfigurable Platforms Programmability for Synchronous Data-Flow Applications.
ACM Trans. Reconfigurable Technol. Syst.
Laurent Gantel, Amel Khiar, Benoît Miramond, Mohamed El Amine Benkhelifa, Lounis Kessal, Fabrice Lemonnier, Jimmy Le Rhun
2011 — conf
Dataflow programming model for reconfigurable computing.
ReCoSoC
Laurent Gantel, Amel Khiar, Benoît Miramond, Mohamed El Amine Benkhelifa, Fabrice Lemonnier, Lounis Kessal
2009 J jnl
Hardware Architecture for Pattern Recognition in Gamma-Ray Experiment.
EURASIP J. Embed. Syst.
Sonia Khatchadourian, Jean-Christophe Prévotet, Lounis Kessal
2008 B conf
Neural network hardware architecture for pattern recognition in the HESS2 project.
ESANN
Narayanan Ramanan, Sonia Khatchadourian, Jean-Christophe Prévotet, Lounis Kessal
2008 J jnl
Reconfigurable computing: design methodology and hardware tasks scheduling for real-time image processing.
J. Real Time Image Process.
Lounis Kessal, Nicolas Abel, Si Mahmoud Karabernou, Didier Demigny
2007 J jnl
Erratum to "Real-time FPGA implementation of Hough Transform using gradient and CORDIC algorithm" [Image and Vision Computing 23 (2005) 1009-1017].
Image Vis. Comput.
Si Mahmoud Karabernou, Lounis Kessal, Fayçal Terranti
2006 — conf
Clear Stream towards Dynamically Reconfigurable Systems on Chip.
ReCoSoC
Nicolas Abel, Lounis Kessal, Sébastien Pillement, Didier Demigny
2004 B conf
Design flexibility using fpga dynamical reconfiguration.
ICIP
Nicolas Abel, Lounis Kessal, Didier Demigny
2003 J jnl
Real-time image processing with dynamically reconfigurable architecture.
Real Time Imaging
Lounis Kessal, Nicolas Abel, Didier Demigny
2001 C conf
Fast Recursive Implementation of the Gaussian Filter.
VLSI-SOC
Didier Demigny, Lounis Kessal, J. Pons
2001 C conf
Reconfigurable Architecture Using High Speed FPGA.
VLSI-SOC
Lounis Kessal, R. Bourguiba, Didier Demigny, N. Boudouani, Si Mahmoud Karabernou
2001 C conf
Two ASIC for Low and Middle Levels of Real Time Image Processing.
VLSI-SOC
P. Lamaty, B. Mazar, Didier Demigny, Lounis Kessal, Si Mahmoud Karabernou
2000 — conf
How to Use High Speed Reconfigurable FPGA for Real Time Image Processing?
CAMP
Didier Demigny, Lounis Kessal, R. Bourguiba, N. Boudouani
2000 B conf
Reconfigurable Hardware for Real Time Image Processing.
ICIP
Lounis Kessal, Didier Demigny, N. Boudouani, R. Bourguiba
1997 — conf
Efficient ASIC and FPGA Implementations of IIR Filters for Real Time Edge Detection.
ICIP (2)
F. G. Lorca, Lounis Kessal, Didier Demigny
1995 B conf
Evaluation of edge detectors performances with a discrete expression of Canny's criteria.
ICIP
Didier Demigny, F. G. Lorca, Lounis Kessal