Lorenzo Ciampolini

15 papers A 2C 1Journal 2Unranked 10

Year	Rank	Type	Title / Venue / Authors
2022	—	`conf`	An Automated Design Methodology for Computational SRAM Dedicated to Highly Data-Centric Applications: Invited Paper. SLIP A. Philippe, Lorenzo Ciampolini, M. Gerbaud, M. Ramirez-Corrales, Valentin Egloff, Bastien Giraud, Jean-Philippe Noël
2021	—	`conf`	A Near-Instantaneous and Non-Invasive Erasure Design Technique to Protect Sensitive Data Stored in Secure SRAMs. ESSCIRC Jean-Philippe Noel, Manuel Pezzin, Jean-Frédéric Christmann, Lorenzo Ciampolini, M. Le Coadou, M. Diallo, Florent Lepin, B. Blampey, Simone Bacles-Min, R. Wacquez, Bastien Giraud
2021	A	`conf`	Storage Class Memory with Computing Row Buffer: A Design Space Exploration. DATE Valentin Egloff, Jean-Philippe Noel, Maha Kooli, Bastien Giraud, Lorenzo Ciampolini, Roman Gauchi, César Fuguet Tortolero, Eric Guthmuller, Mathieu Moreau, Jean-Michel Portal
2018	J	`jnl`	A 128 kb 7T SRAM Using a Single-Cycle Boosting Mechanism in 28-nm FD-SOI. IEEE Trans. Circuits Syst. I Regul. Pap. Babak Mohammadi, Oskar Andersson, Joseph Nguyen, Lorenzo Ciampolini, Andreia Cathelin, Joachim Neves Rodrigues
2017	—	`conf`	High-yield design of high-density SRAM for low-voltage and low-leakage operations. DFT Kedar Janardan Dhori, Hitesh Chawla, Ashish Kumar, Prashant Pandey, Promod Kumar, Lorenzo Ciampolini, Florian Cacho, Damien Croain
2016	—	`conf`	28nm FDSOI technology sub-0.6V SRAM Vmin assessment for ultra low voltage applications. VLSI Circuits Rossella Ranica, Nicolas Planes, Vincent Huard, Olivier Weber, Daniel Noblet, Damien Croain, Fabien Giner, Sylvie Naudet, P. Mergault, S. Ibars, A. Villaret, Maryline Parra, Sébastien Haendler, M. Quoirin, Florian Cacho, C. Julien, F. Terrier, Lorenzo Ciampolini, David Turgis, Christophe Lecocq, Franck Arnaud
2016	—	`conf`	A 128 kb single-bitline 8.4 fJ/bit 90MHz at 0.3V 7T sense-amplifierless SRAM in 28 nm FD-SOI. ESSCIRC Babak Mohammadi, Oskar Andersson, Joseph Nguyen, Lorenzo Ciampolini, Andreia Cathelin, Joachim Neves Rodrigues
2016	A	`conf`	Efficient yield estimation through generalized importance sampling with application to NBL-assisted SRAM bitcells. ICCAD Lorenzo Ciampolini, Jean-Christophe Lafont, Faress Tissafi Drissi, Jean-Paul Morin, David Turgis, Xavier Jonsson, Cyril Desclèves, Joseph Nguyen
2016	—	`conf`	RAPIDO Testing and Modeling of Assisted Write and Read Operations for SRAMs. NATW Joseph Nguyen, David Turgis, David Bonciani, Brice Lhomme, Yann Carminati, Olivier Callen, Guillaume Guirleo, Lorenzo Ciampolini, Gérard Ghibaudo
2015	—	`conf`	Design and performance parameters of an ultra-low voltage, single supply 32bit processor implemented in 28nm FDSOI technology. ISQED Sylvain Clerc, Fady Abouzeid, Darayus Adil Patel, Jean-Marc Daveau, Cyril Bottoni, Lorenzo Ciampolini, Fabien Giner, David Meyer, Robin Wilson, Philippe Roche, Sylvie Naudet, Arnaud Virazel, Alberto Bosio, Patrick Girard
2014	—	`conf`	Impact of Random Telegraph Signals on 6T high-density SRAM in 28nm UTBB FD-SOI. ESSDERC Kaya Can Akyel, Lorenzo Ciampolini, Olivier Thomas, David Turgis, Gérard Ghibaudo
2014	J	`jnl`	Scalable 0.35 V to 1.2 V SRAM Bitcell Design From 65 nm CMOS to 28 nm FDSOI. IEEE J. Solid State Circuits Fady Abouzeid, Audrey Bienfait, Kaya Can Akyel, Anis Feki, Sylvain Clerc, Lorenzo Ciampolini, Fabien Giner, Robin Wilson, Philippe Roche
2013	C	`conf`	Multiple-pulse dynamic stability and failure analysis of low-voltage 6T-SRAM bitcells in 28nm UTBB-FDSOI. ISCAS Kaya Can Akyel, Lorenzo Ciampolini, Olivier Thomas, Bertrand Pelloux-Prayer, Shishir Kumar, Philippe Flatresse, Christophe Lecocq, Gérard Ghibaudo
2013	—	`conf`	Scalable 0.35V to 1.2V SRAM bitcell design from 65nm CMOS to 28nm FDSOI. ESSCIRC Fady Abouzeid, Audrey Bienfait, Kaya Can Akyel, Sylvain Clerc, Lorenzo Ciampolini, Philippe Roche
2012	—	`conf`	Proposal of a new ultra low leakage 10T sub threshold SRAM bitcell. ISOCC Anis Feki, Bruno Allard, David Turgis, Jean-Christophe Lafont, Lorenzo Ciampolini