Lorena Anghel

134 papers A 14B 7C 35Misc 8Journal 28Unranked 41
YearRankTypeTitle / Venue / Authors
2026 — conf
ATPG-Compliant Digital Modeling of MRAM for Cell-Aware Testing.
LASCAS
Arshid Nisar, Lorena Anghel, Gregory di Pendina
2026 — conf
Design of a Low-Power High-Density Analog in-Memory Computing Accelerator Using 18 Nm FD-SOI Phase-Change Memory.
LATS
V. Viollet, Guillaume Prenat, A. Al Muktash, C. Popon, Lorena Anghel, X. Lecoq
2025 A conf
Enabling a Portable Brain Computer Interface for Rehabilitation of Spinal Cord Injuries.
DATE
Adrian Evans, Victor Roux-Sibillon, Joe Saad, Ivan Miro-Panades, Tetiana Aksenova, Lorena Anghel
2025 C conf
Fault Modeling and Testing of Spin-Orbit Torque-Based Multipillar Memory Cell.
VLSI-SoC
Arshid Nisar, Lorena Anghel, Gregory di Pendina
2025 — conf
Low-Power Feature Extraction for BCI Applications Using Approximate Continuous Wavelet Transform.
BCI
Joe Saad, Adrian Evans, Ivan Miro-Panades, Tetiana Aksenova, Lorena Anghel
2025 — conf
Temperature and Drift-Aware High-Level PCM-based Array Model for Reliable Hardware IMC Design.
IRPS
V. Viollet, E. Esmanhotto, M. Allegra, Matteo Baldo, Guillaume Prenat, Lorena Anghel, X. Lecoq
2024 J jnl
Backpropagation-Based Learning Techniques for Deep Spiking Neural Networks: A Survey.
IEEE Trans. Neural Networks Learn. Syst.
Manon Dampfhoffer, Thomas Mesquida, Alexandre Valentian, Lorena Anghel
2024 A conf
Enhancing Reliability of Neural Networks at the Edge: Inverted Normalization with Stochastic Affine Transformations.
DATE
Soyed Tuhin Ahmed, Kamal Danouchi, Guillaume Prenat, Lorena Anghel, Mehdi B. Tahoori
2024 J jnl
Enhancing Reliability of Neural Networks at the Edge: Inverted Normalization with Stochastic Affine Transformations.
CoRR
Soyed Tuhin Ahmed, Kamal Danouchi, Guillaume Prenat, Lorena Anghel, Mehdi B. Tahoori
2024 A conf
NeuSpin: Design of a Reliable Edge Neuromorphic System Based on Spintronics for Green AI.
DATE
Soyed Tuhin Ahmed, Kamal Danouchi, Guillaume Prenat, Lorena Anghel, Mehdi B. Tahoori
2024 J jnl
NeuSpin: Design of a Reliable Edge Neuromorphic System Based on Spintronics for Green AI.
CoRR
Soyed Tuhin Ahmed, Kamal Danouchi, Guillaume Prenat, Lorena Anghel, Mehdi B. Tahoori
2024 B conf
Testing Spintronics Implemented Monte Carlo Dropout-Based Bayesian Neural Networks.
ETS
Soyed Tuhin Ahmed, Kamal Danouchi, Michael Hefenbrock, Guillaume Prenat, Lorena Anghel, Mehdi B. Tahoori
2024 J jnl
Testing Spintronics Implemented Monte Carlo Dropout-Based Bayesian Neural Networks.
CoRR
Soyed Tuhin Ahmed, Michael Hefenbrock, Guillaume Prenat, Lorena Anghel, Mehdi B. Tahoori
2023 J jnl
A tunable and versatile 28nm FD-SOI crossbar output circuit for low power analog SNN inference with eNVM synapses.
CoRR
Joao Henrique Quintino Palhares, Yann Beilliard, Jury Sandrini, Franck Arnaud, Kevin Garello, Guillaume Prenat, Lorena Anghel, Fabien Alibart, Dominique Drouin, Philippe Galy
2023 J jnl
Are SNNs Really More Energy-Efficient Than ANNs? an In-Depth Hardware-Aware Study.
IEEE Trans. Emerg. Top. Comput. Intell.
Manon Dampfhoffer, Thomas Mesquida, Alexandre Valentian, Lorena Anghel
2023 — conf
Evaluating the Impact of Aging on Path-Delay Self-Test Libraries.
DFT
Riccardo Cantoro, Sandro Sartoni, Matteo Sonza Reorda, Lorena Anghel, Michele Portolan
2023 B conf
Improving the Robustness of Neural Networks to Noisy Multi-Level Non-Volatile Memory-based Synapses.
IJCNN
Manon Dampfhoffer, Joel Minguet Lopez, Thomas Mesquida, Alexandre Valentian, Lorena Anghel
2023 Misc conf
Leveraging Sparsity with Spiking Recurrent Neural Networks for Energy-Efficient Keyword Spotting.
ICASSP
Manon Dampfhoffer, Thomas Mesquida, Emmanuel Hardy, Alexandre Valentian, Lorena Anghel
2023 C conf
Minimum SRAM Retention Voltage: Insight about optimizing Power Efficiency across Temperature Profile, Process Variation and Aging.
IOLTS
Yunus Emre Aslan, Florian Cacho, T. Kumar, D. K. Janardan, A. Kumar, F. Giner, M. Faurichon, Lorena Anghel
2023 B conf
On Using Cell-Aware Methodology for SRAM Bit Cell Testing.
ETS
Xhesila Xhafa, Aymen Ladhar, Eric Faehn, Lorena Anghel, Gregory di Pendina, Patrick Girard, Arnaud Virazel
2023 — conf
Robustness and Power Efficiency in Spin-Orbit Torque-Based Probabilistic Logic Circuits.
ISVLSI
Kamal Danouchi, Guillaume Prenat, Philippe Talatchian, Louis Hutin, Lorena Anghel
2023 A conf
Scalable Spintronics-based Bayesian Neural Network for Uncertainty Estimation.
DATE
Soyed Tuhin Ahmed, Kamal Danouchi, Michael Hefenbrock, Guillaume Prenat, Lorena Anghel, Mehdi B. Tahoori
2023 J jnl
Scale-Dropout: Estimating Uncertainty in Deep Neural Networks Using Stochastic Scale.
CoRR
Soyed Tuhin Ahmed, Kamal Danouchi, Michael Hefenbrock, Guillaume Prenat, Lorena Anghel, Mehdi B. Tahoori
2023 J jnl
Self-Test Library Generation for In-Field Test of Path Delay Faults.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Lorena Anghel, Riccardo Cantoro, Riccardo Masante, Michele Portolan, Sandro Sartoni, Matteo Sonza Reorda
2023 J jnl
Spatial-SpinDrop: Spatial Dropout-based Binary Bayesian Neural Network with Spintronics Implementation.
CoRR
Soyed Tuhin Ahmed, Kamal Danouchi, Michael Hefenbrock, Guillaume Prenat, Lorena Anghel, Mehdi B. Tahoori
2023 J jnl
SpinBayes: Algorithm-Hardware Co-Design for Uncertainty Estimation Using Bayesian In-Memory Approximation on Spintronic-Based Architectures.
ACM Trans. Embed. Comput. Syst.
Soyed Tuhin Ahmed, Kamal Danouchi, Michael Hefenbrock, Guillaume Prenat, Lorena Anghel, Mehdi B. Tahoori
2023 J jnl
SpinDrop: Dropout-Based Bayesian Binary Neural Networks With Spintronic Implementation.
IEEE J. Emerg. Sel. Topics Circuits Syst.
Soyed Tuhin Ahmed, Kamal Danouchi, Christopher Münch, Guillaume Prenat, Lorena Anghel, Mehdi B. Tahoori
2023 J jnl
Spintronic Memristor-Based Binarized Ensemble Convolutional Neural Network Architectures.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Ghislain Takam Tchendjou, Kamal Danouchi, Guillaume Prenat, Lorena Anghel
2022 J jnl
A Fast, Energy Efficient and Tunable Magnetic Tunnel Junction Based Bitstream Generator for Stochastic Computing.
IEEE Trans. Circuits Syst. I Regul. Pap.
Etienne Becle, Guillaume Prenat, Philippe Talatchian, Lorena Anghel, Ioan Lucian Prejbeanu
2022 — conf
Binary Bayesian Neural Networks for Efficient Uncertainty Estimation Leveraging Inherent Stochasticity of Spintronic Devices.
NANOARCH
Soyed Tuhin Ahmed, Kamal Danouchi, Christopher Münch, Guillaume Prenat, Lorena Anghel, Mehdi B. Tahoori
2022 J jnl
Design-Time Exploration for Process, Environment and Aging Compensation Techniques for Low Power Reliable-Aware Design.
IEEE Trans. Emerg. Top. Comput.
Lorena Anghel, Florian Cacho
2022 — conf
Electrical Coupling of Perpendicular Superparamagnetic Tunnel Junctions for Probabilistic Computing.
NANOARCH
Nhat-Tan Phan, Lucile Soumah, Ahmed Sidi El Valli, Louis Hutin, Lorena Anghel, Ursula Ebels, Philippe Talatchian
2022 — conf
Improving DNN Fault Tolerance in Semantic Segmentation Applications.
DFT
Stéphane Burel, Adrian Evans, Lorena Anghel
2022 — conf
Investigating Current-Based and Gating Approaches for Accurate and Energy-Efficient Spiking Recurrent Neural Networks.
ICANN (3)
Manon Dampfhoffer, Thomas Mesquida, Alexandre Valentian, Lorena Anghel
2022 — conf
Spin Orbit Torque-based Crossbar Array for Error Resilient Binary Convolutional Neural Network.
LATS
Kamal Danouchi, Guillaume Prenat, Lorena Anghel
2021 — conf
Fast Behavioral VerilogA Compact Model for Stochastic MTJ.
ESSDERC
Etienne Becle, Philippe Talatchian, Guillaume Prenat, Lorena Anghel, Ioan Lucian Prejbeanu
2021 C conf
MOZART: Masking Outputs with Zeros for Architectural Robustness and Testing of DNN Accelerators.
IOLTS
Stéphane Burel, Adrian Evans, Lorena Anghel
2021 — conf
Monitoring Setup and Hold Timing Limits.
IRPS
Florian Cacho, Lorena Anghel, Xavier Federspiel
2021 — conf
Zero-Overhead Protection for CNN Weights.
DFT
Stéphane Burel, Adrian Evans, Lorena Anghel
2020 C conf
A Comprehensive End-to-end Solution for a Secure and Dynamic Mixed-signal 1687 System.
IOLTS
Michele Portolan, R. Silveira Feitoza, Ghislain Takam Tchendjou, Vincent Reynaud, Kalpana Senthamarai Kannan, Manuel J. Barragán, Emmanuel Simeu, Paolo Maistri, Lorena Anghel, Régis Leveugle, Salvador Mir
2020 A conf
New Perspectives on Core In-field Path Delay Test.
ITC
Riccardo Cantoro, Dario Foti, Sandro Sartoni, Matteo Sonza Reorda, Lorena Anghel, Michele Portolan
2020 J jnl
Stuck-At Fault Mitigation of Emerging Technologies Based Switching Lattices.
J. Electron. Test.
Lorena Anghel, Anna Bernasconi, Valentina Ciriani, Luca Frontini, Gabriella Trucco, Elena I. Vatajelu
2019 — conf
Fault Mitigation of Switching Lattices under the Stuck-At-Fault Model.
LATS
Lorena Anghel, Anna Bernasconi, Valentina Ciriani, Luca Frontini, Gabriella Trucco, Elena I. Vatajelu
2019 Misc conf
Flexi-AES: A Highly-Parameterizable Cipher for a Wide Range of Design Constraints.
FCCM
Sergiu Mosanu, Xinfei Guo, Mohamed El-Hadedy, Lorena Anghel, Mircea Stan
2019 A conf
Hidden-Delay-Fault Sensor for Test, Reliability and Security.
DATE
Giorgio Di Natale, Elena-Ioana Vatajelu, Kalpana Senthamarai Kannan, Lorena Anghel
2019 — conf
Rebooting Computing: The Challenges for Test and Reliability.
DFT
Alberto Bosio, Ian O'Connor, Gennaro Severino Rodrigues, Fernanda Lima Kastensmidt, Elena I. Vatajelu, Giorgio Di Natale, Lorena Anghel, Surya Nagarajan, Moritz Fieback, Said Hamdioui
2019 Misc conf
Special Session: Reliability of Hardware-Implemented Spiking Neural Networks (SNN).
VTS
Elena-Ioana Vatajelu, Giorgio Di Natale, Lorena Anghel
2018 — conf
Integrated Synthesis Methodology for Crossbar Arrays.
NANOARCH
Muhammed Ceylan Morgül, Onur Tunali, Mustafa Altun, Luca Frontini, Valentina Ciriani, Elena-Ioana Vatajelu, Lorena Anghel, Csaba Andras Moritz, Mircea R. Stan, Dan Alexandrescu
2018 — conf
Investigation of speed sensors accuracy for process and aging compensation.
IRPS
Riddhi Jitendrakumar Shah, Florian Cacho, Vincent Huard, Souhir Mhira, D. Arora, Pankaj Agarwal, Shubham Kumar, S. Balaraman, Bijoy Kumar Singh, Lorena Anghel
2018 A conf
NBTI aged cell rejuvenation with back biasing and resulting critical path reordering for digital circuits in 28nm FDSOI.
DATE
Ajith Sivadasan, Riddhi Jitendrakumar Shah, Vincent Huard, Florian Cacho, Lorena Anghel
2018 C conf
Neuromorphic Computing - From Robust Hardware Architectures to Testing Strategies.
VLSI-SoC
Lorena Anghel, Denys Ly, Giorgio Di Natale, Benoît Miramond, Elena-Ioana Vatajelu, Elisa Vianello
2018 C conf
Resistive and Spintronic RAMs: Device, Simulation, and Applications.
IOLTS
Elena-Ioana Vatajelu, Lorena Anghel, Jean-Michel Portal, Marc Bocquet, Guillaume Prenat
2018 J jnl
Test and Reliability in Approximate Computing.
J. Electron. Test.
Lorena Anghel, Mounir Benabdenbi, Alberto Bosio, Marcello Traiola, Elena-Ioana Vatajelu
2017 — conf
Fully-connected single-layer STT-MTJ-based spiking neural network under process variability.
NANOARCH
Elena-Ioana Vatajelu, Lorena Anghel
2017 C conf
Investigation of critical path selection for in-situ monitors insertion.
IOLTS
Florian Cacho, Ahmed Benhassain, Riddhi Jitendrakumar Shah, Souhir Mhira, Vincent Huard, Lorena Anghel
2017 J jnl
Logic synthesis and testing techniques for switching nano-crossbar arrays.
Microprocess. Microsystems
Dan Alexandrescu, Mustafa Altun, Lorena Anghel, Anna Bernasconi, Valentina Ciriani, Luca Frontini, Mehdi Baradaran Tahoori
2017 C conf
Reliability analysis of MTJ-based functional module for neuromorphic computing.
IOLTS
Elena-Ioana Vatajelu, Lorena Anghel
2017 A conf
Workload dependent reliability timing analysis flow.
DATE
Ajith Sivadasan, Armelle Notin, Vincent Huard, Etienne Maurin, Souhir Mhira, Florian Cacho, Lorena Anghel
2016 B conf
A hybrid algorithm to conservatively check the robustness of circuits.
ETS
Niels Thole, Lorena Anghel, Görschwin Fey
2016 C conf
Activity profiling: Review of different solutions to develop reliable and performant design.
IOLTS
Florian Cacho, Ahmed Benhassain, Souhir Mhira, Ajith Sivadasan, Vincent Huard, P. Cathelin, Vincent Knopik, Abhishek Jain, C. R. Parthasarathy, Lorena Anghel
2016 — conf
Early failure prediction by using in-situ monitors: Implementation and application results.
ERMAVSS@DATE
Ahmed Benhassain, Florian Cacho, Vincent Huard, Lorena Anghel
2016 Misc conf
Early system failure prediction by using aging in situ monitors: Methodology of implementation and application results.
VTS
Lorena Anghel, Ahmed Benhassain, Ajith Sivadasan, Florian Cacho, Vincent Huard
2016 — conf
In-situ slack monitors: taking up the challenge of on-die monitoring of variability and reliability.
IVSW
Ahmed Benhassain, Souhir Mhira, Florian Cacho, Vincent Huard, Lorena Anghel
2016 — conf
Multi-context non-volatile content addressable memory using magnetic tunnel junctions.
NANOARCH
Erya Deng, Lorena Anghel, Guillaume Prenat, Weisheng Zhao
2016 A conf
Study of workload impact on BTI HCI induced aging of digital circuits.
DATE
Ajith Sivadasan, Florian Cacho, Sidi Ahmed Benhassain, Vincent Huard, Lorena Anghel
2016 C conf
Synthesis and Performance Optimization of a Switching Nano-Crossbar Computer.
DSD
Dan Alexandrescu, Mustafa Altun, Lorena Anghel, Anna Bernasconi, Valentina Ciriani, Luca Frontini, Mehdi Baradaran Tahoori
2016 — conf
Workload Impact on BTI HCI Induced Aging of Digital Circuits: A System level Analysis.
ERMAVSS@DATE
Ajith Sivadasan, Florian Cacho, Sidi Ahmed Benhassain, Vincent Huard, Lorena Anghel
2015 — conf
Application-independent testing of multilevel interconnect in mesh-based FPGAs.
DTIS
Saif-Ur Rehman, Mounir Benabdenbi, Lorena Anghel
2015 J jnl
Dependable Multicore Architectures at Nanoscale: The View From Europe.
IEEE Des. Test
Marco Ottavi, Salvatore Pontarelli, Dimitris Gizopoulos, Cristiana Bolchini, Maria K. Michael, Lorena Anghel, Mehdi Baradaran Tahoori, Antonis M. Paschalis, Pedro Reviriego, Oliver Bringmann, Viacheslav Izosimov, Hans A. R. Manhaeve, Christos Strydis, Said Hamdioui
2015 A conf
Digital circuits reliability with in-situ monitors in 28nm fully depleted SOI.
DATE
M. Saliva, Florian Cacho, Vincent Huard, X. Federspiel, D. Angot, Ahmed Benhassain, Alain Bravaix, Lorena Anghel
2015 — conf
Impact of gate oxide breakdown in logic gates from 28nm FDSOI CMOS technology.
IRPS
M. Saliva, Florian Cacho, Cheikh Ndiaye, Vincent Huard, D. Angot, Alain Bravaix, Lorena Anghel
2015 — conf
Timing in-situ monitors: Implementation strategy and applications results.
CICC
Ahmed Benhassain, Florian Cacho, Vincent Huard, M. Saliva, Lorena Anghel, C. R. Parthasarathy, Abhishek Jain, Fabien Giner
2014 C conf
Cost-efficient of a cluster in a mesh SRAM-based FPGA.
IOLTS
Saif-Ur Rehman, Mounir Benabdenbi, Lorena Anghel
2014 J jnl
Editorial.
Microprocess. Microsystems
Lorena Anghel, Cristiana Bolchini, Salvatore Pontarelli
2014 C conf
Exploring the state dependent SET sensitivity of asynchronous logic - The muller-pipeline example.
ICCD
Andreas Steininger, Varadan Savulimedu Veeravalli, Dan Alexandrescu, Enrico Costenaro, Lorena Anghel
2014 J jnl
Fault-tolerant adaptive routing under an unconstrained set of node and link failures for many-core systems-on-chip.
Microprocess. Microsystems
Michael G. Dimopoulos, Yi Gang, Lorena Anghel, Mounir Benabdenbi, Nacer-Eddine Zergainoh, Michael Nicolaidis
2014 — conf
Impact of Cluster Size on Routability, Testability and Robustness of a Cluster in a Mesh FPGA.
ISVLSI
Saif-Ur Rehman, Adrien Blanchardon, Arwa Ben Dhia, Mounir Benabdenbi, Roselyne Chotin-Avot, Lirida A. B. Naviner, Lorena Anghel, Habib Mehrez, Emna Amouri, Zied Marrakchi
2014 — conf
System on chip project: Integration of a Motion-JPEG video decoder.
EWME
Lorena Anghel, Mounir Benabdenbi, Frédéric Pétrot
2013 — conf
BIST for logic and local interconnect resources in a novel mesh of cluster FPGA.
DFTS
Saif-Ur Rehman, Mounir Benabdenbi, Lorena Anghel
2013 C conf
Fault-tolerant adaptive routing under permanent and temporary failures for many-core systems-on-chip.
IOLTS
Michael G. Dimopoulos, Yi Gang, Mounir Benabdenbi, Lorena Anghel, Nacer-Eddine Zergainoh, Michael Nicolaidis
2013 J jnl
Reliability of TSV interconnects: Electromigration, thermal cycling, and impact on above metal level dielectric.
Microelectron. Reliab.
Thomas Frank, Stéphane Moreau, Cédrick Chappaz, Patrick Leduc, Lucile Arnaud, Aurélie Thuaire, Emmanuel Chery, F. Lorut, Lorena Anghel, Gilles Poupon
2012 J jnl
CSL: Configurable Fault Tolerant Serial Links for Inter-die Communication in 3D Systems.
J. Electron. Test.
Vladimir Pasca, Lorena Anghel, Michael Nicolaidis, Mounir Benabdenbi
2012 A conf
Design for test and reliability in ultimate CMOS.
DATE
Michael Nicolaidis, Lorena Anghel, Nacer-Eddine Zergainoh, Yervant Zorian, Tanay Karnik, Keith A. Bowman, James W. Tschanz, Shih-Lien Lu, Carlos Tokunaga, Arijit Raychowdhury, Muhammad M. Khellah, Jaydeep P. Kulkarni, Vivek De, Dimiter Avresky
2012 C conf
Efficient link-level error resilience in 3D NoCs.
DDECS
Vladimir Pasca, Saif-Ur Rehman, Lorena Anghel, Mounir Benabdenbi
2012 J jnl
Kth-Aggressor Fault (KAF)-based Thru-Silicon-Via Interconnect Built-In Self-Test and Diagnosis.
J. Electron. Test.
Vladimir Pasca, Lorena Anghel, Mounir Benabdenbi
2012 C conf
Through-silicon-via built-in self-repair for aggressive 3D integration.
IOLTS
Michael Nicolaidis, Vladimir Pasca, Lorena Anghel
2011 J jnl
Adaptive inter-layer message routing in 3D networks-on-chip.
Microprocess. Microsystems
Claudia Rusu, Lorena Anghel, Dimiter Avresky
2011 — conf
Bottom-up digital system-level reliability modeling.
CICC
N. Ruiz Amador, Vincent Huard, E. Pion, Florian Cacho, Damien Croain, V. Robert, Sylvain Engels, Philippe Flatresse, Lorena Anghel
2011 — conf
Configurable Thru-Silicon-Via interconnect Built-In Self-Test and diagnosis.
LATW
Vladimir Pasca, Lorena Anghel, Mounir Benabdenbi
2011 B conf
Efficient Fault Detection Architecture Design of Latch-Based Low Power DSP/MCU Processor.
ETS
Hai Yu, Michael Nicolaidis, Lorena Anghel, Nacer-Eddine Zergainoh
2011 B conf
I-BIRAS: Interconnect Built-In Self-Repair and Adaptive Serialization in 3D Integrated Systems.
ETS
Michael Nicolaidis, Vladimir Pasca, Lorena Anghel
2011 C conf
Memory BIST with address programmability.
IOLTS
Aymen Fradi, Michael Nicolaidis, Lorena Anghel
2010 B conf
Configurable fault-tolerant link for inter-die communication in 3D on-chip networks.
ETS
Vladimir Pasca, Lorena Anghel, Claudia Rusu, Mounir Benabdenbi
2010 C conf
Configurable serial fault-tolerant link for communication in 3D integrated systems.
IOLTS
Vladimir Pasca, Lorena Anghel, Claudia Rusu, Mounir Benabdenbi
2010 A conf
Error resilience of intra-die and inter-die communication with 3D spidergon STNoC.
DATE
Vladimir Pasca, Lorena Anghel, Claudia Rusu, Riccardo Locatelli, Massimo Coppola
2010 — conf
Fault tolerant communication in 3D integrated systems.
DSN Workshops
Vladimir Pasca, Lorena Anghel, Mounir Benabdenbi
2010 C conf
Interconnect Built-In Self-Repair and Adaptive-Serialization (I-BIRAS) for 3D integrated systems.
IOLTS
Michael Nicolaidis, Vladimir Pasca, Lorena Anghel
2010 C conf
RILM: Reconfigurable inter-layer routing mechanism for 3D multi-layer networks-on-chip.
IOLTS
Claudia Rusu, Lorena Anghel, Dimiter Avresky
2009 — conf
An effective approach to detect logic soft errors in digital circuits based on GRAAL.
ISQED
Hai Yu, Michael Nicolaidis, Lorena Anghel
2009 A conf
HOT TOPIC - Concurrent SoC development and end-to-end planning.
DATE
Lorena Anghel
2008 C conf
Communication Aware Recovery Configurations for Networks-on-Chip.
IOLTS
Claudia Rusu, Cristian Grecu, Lorena Anghel
2008 — conf
Coordinated versus Uncoordinated Checkpoint Recovery for Network-on-Chip Based Systems.
DELTA
Claudia Rusu, Cristian Grecu, Lorena Anghel
2008 C conf
Digital Implementation of a BIST Method based on Binary Observations.
DSD
Christophe Le Blanc, Éric Colinet, Jérôme Juillard, Lorena Anghel
2008 C conf
Improving the scalability of checkpoint recovery for networks-on-chip.
ISCAS
Claudia Rusu, Cristian Grecu, Lorena Anghel
2007 J jnl
A Case Study on Phase-Locked Loop Automatic Layout Generation and Transient Fault Injection Analysis.
J. Electron. Test.
Cristiano Lazzari, Ricardo A. L. Reis, Lorena Anghel
2007 J jnl
CNTFET Modeling and Reconfigurable Logic-Circuit Design.
IEEE Trans. Circuits Syst. I Regul. Pap.
Ian O'Connor, Junchen Liu, Frédéric Gaffiot, Fabien Prégaldiny, Christophe Lallement, Cristell Maneux, Johnny Goguet, Sébastien Fregonese, Thomas Zimmer, Lorena Anghel, Trong-Trinh Dang, Régis Leveugle
2007 Misc conf
Defects Tolerant Logic Gates for Unreliable Future Nanotechnologies.
IWANN
Lorena Anghel, Michael Nicolaidis
2007 C conf
Efficient timing closure with a transistor level design flow.
VLSI-SoC
Cristiano Lazzari, Cristiano Santos, Adriel Ziesemer, Lorena Anghel, Ricardo Reis
2007 C conf
Essential Fault-Tolerance Metrics for NoC Infrastructures.
IOLTS
Cristian Grecu, Lorena Anghel, Partha Pratim Pande, André Ivanov, Resve A. Saleh
2007 C conf
Multiple Event Transient Induced by Nuclear Reactions in CMOS Logic Cells.
IOLTS
Claudia Rusu, Antonin Bougerol, Lorena Anghel, Cécile Weulersse, Nadine Buard, S. Benhammadi, Nicolas Renaud, Guillaume Hubert, Frederic Wrobel, Thierry Carrière, Rémi Gaillard
2006 C conf
From Nuclear Reaction to System Failures: Can We Address All Levels of Soft Errors Accurately?
IOLTS
Lorena Anghel, Michael Nicolaidis, Nadine Buard
2006 — conf
Multiple Defect Tolerant Devices for Unreliable Future Nanotechnologies.
LATW
Lorena Anghel, Cristiano Lazzari, Michael Nicolaidis
2006 C conf
Phase-Locked Loop Automatic Layout Generation and Transient Fault Injection Analysis: A Case Study.
IOLTS
Cristiano Lazzari, Ricardo A. L. Reis, Lorena Anghel
2006 C conf
Prediction of Transient Induced by Neutron/Proton in CMOS Combinational Logic Cells.
IOLTS
Guillaume Hubert, Antonin Bougerol, Florent Miller, Nadine Buard, Lorena Anghel, Thierry Carrière, Frederic Wrobel, Rémi Gaillard
2005 C conf
A Transistor Placement Technique Using Genetic Algorithm and Analytical Programming.
VLSI-SoC
Cristiano Lazzari, Lorena Anghel, Ricardo Reis
2005 C conf
Evaluation of SET and SEU Effects at Multiple Abstraction Levels.
IOLTS
Lorena Anghel, Régis Leveugle, Pierre Vanhauwaert
2005 J jnl
Memory Defect Tolerance Architectures for Nanotechnologies.
J. Electron. Test.
Michael Nicolaidis, Lorena Anghel, Nadir Achouri
2005 C conf
On Implementing a Soft Error Hardening Technique by Using an Automatic Layout Generator: Case Study.
IOLTS
Cristiano Lazzari, Lorena Anghel, Ricardo A. L. Reis
2005 C conf
Simulation and Mitigation of Single Event Effects.
IOLTS
Lorena Anghel, Michael Nicolaidis
2004 Misc conf
A Diversified Memory Built-In Self-Repair Approach for Nanotechnologies.
VTS
Michael Nicolaidis, Nadir Achouri, Lorena Anghel
2004 — conf
Coupling Different Methodologies to Validate Obsolete Microprocessors.
DFT
Lorena Anghel, Ernesto Sánchez, Matteo Sonza Reorda, Giovanni Squillero, Raoul Velazco
2004 C conf
Evaluation of Memory Built-in Self Repair Techniques for High Defect Density Technologie.
PRDC
Lorena Anghel, Nadir Achouri, Michael Nicolaidis
2004 J jnl
Simulating Single Event Transients in VDSM ICs for Ground Level Radiation.
J. Electron. Test.
Dan Alexandrescu, Lorena Anghel, Michael Nicolaidis
2003 — conf
A Memory Built-In Self-Repair for High Defect Densities Based on Error Polarities.
DFT
Michael Nicolaidis, Nadir Achouri, Lorena Anghel
2003 C conf
A Methodology for Test Replacement Solutions of Obsolete Processors.
IOLTS
Raoul Velazco, Lorena Anghel, S. Saleh
2003 C conf
Memory Built-In Self-Repair for Nanotechnologies.
IOLTS
Michael Nicolaidis, Nadir Achouri, Lorena Anghel
2003 — conf
Preliminary Validation of an Approach Dealing with Processor Obsolescence.
DFT
Lorena Anghel, Raoul Velazco, S. Saleh, S. Deswaertes, A. El Moucary
2002 — conf
New Methods for Evaluating the Impact of Single Event Transients in VDSM ICs.
DFT
Dan Alexandrescu, Lorena Anghel, Michael Nicolaidis
2002 — conf
Simulating Single Event Transients in VDSM ICs for Ground Level Radiation.
LATW
Dan Alexandrescu, Lorena Anghel, Michael Nicolaidis
2001 — —
Les limites technologiques du silicium et tolérance aux fautes. (Fault tolerance versus technological limitations of silicon).
Lorena Anghel
2000 A conf
Cost Reduction and Evaluation of a Temporary Faults Detecting Technique.
DATE
Lorena Anghel, Michael Nicolaidis
2000 — conf
Evaluation of a Soft Error Tolerance Technique Based on Time and/or Space Redundancy.
SBCCI
Lorena Anghel, Dan Alexandrescu, Michael Nicolaidis
2000 Misc conf
Self-Checking Circuits versus Realistic Faults in Very Deep Submicron.
VTS
Lorena Anghel, Michael Nicolaidis, Issam Alzaher-Noufal
1999 Misc conf
Built-In Current Sensor for IDDQ Testing in Deep Submicron CMOS.
VTS
Th. Calin, Lorena Anghel, Michael Nicolaidis