Logan M. Rakai

18 papers C 1Journal 9Unranked 8
YearRankTypeTitle / Venue / Authors
2017 J jnl
A Multiobjective Cooptimization of Buffer and Wire Sizes in High-Performance Clock Trees.
IEEE Trans. Circuits Syst. II Express Briefs
Amin Farshidi, Laleh Behjat, Logan M. Rakai, David T. Westwick
2016 J jnl
A fast force-directed simulated annealing for 3D IC partitioning.
Integr.
Aysa Fakheri Tabrizi, Laleh Behjat, William Swartz, Logan M. Rakai
2015 — conf
A Detailed Routing-Aware Detailed Placement Technique.
ISVLSI
Aysa Fakheri Tabrizi, Nima Karimpour Darav, Logan M. Rakai, Andrew A. Kennings, William Swartz, Laleh Behjat
2014 — conf
GPU-Accelerated Solutions to Optimal Power Flow Problems.
HICSS
Logan M. Rakai, William D. Rosehart
2014 J jnl
Optimal gate sizing using a self-tuning multi-objective framework.
Integr.
Amin Farshidi, Logan M. Rakai, Laleh Behjat, David T. Westwick
2014 J jnl
Variation-Aware Geometric Programming Models for the Clock Network Buffer Sizing Problem.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Logan M. Rakai, Amin Farshidi, David T. Westwick, Laleh Behjat
2013 J jnl
A new a priori net length estimation technique for integrated circuits using radial basis functions.
Comput. Electr. Eng.
Amin Farshidi, Logan M. Rakai, Bardia Samimi, Laleh Behjat, David T. Westwick
2013 — conf
A self-tuning multi-objective optimization framework for geometric programming with gate sizing applications.
ACM Great Lakes Symposium on VLSI
Amin Farshidi, Logan M. Rakai, Laleh Behjat, David T. Westwick
2013 — conf
Buffer sizing for clock networks using robust geometric programming considering variations in buffer sizes.
ISPD
Logan M. Rakai, Amin Farshidi, Laleh Behjat, David T. Westwick
2012 J jnl
A New Length-Based Algebraic Multigrid Clustering Algorithm.
VLSI Design
Logan M. Rakai, Amin Farshidi, Laleh Behjat, David T. Westwick
2012 J jnl
An algebraic multigrid-based algorithm for circuit clustering.
Appl. Math. Comput.
Logan M. Rakai, Laleh Behjat, Sebastian Martin, José A. Aguado
2012 — conf
Parallel clock tree synthesis.
CCECE
Logan M. Rakai, Laleh Behjat
2011 J jnl
A pre-placement individual net length estimation model and an application for modern circuits.
Integr.
Amin Farshidi, Laleh Behjat, Logan M. Rakai, Bahareh Fathi
2011 — conf
Wirelength and congestion estimation for routability-driven placement.
SLIP
Yang-Yang Li, Logan M. Rakai, Laleh Behjat, Bill Swartz
2009 J jnl
A Multilevel Congestion-Based Global Router.
VLSI Design
Logan M. Rakai, Laleh Behjat, Shawki Areibi, Tamás Terlaky
2009 — conf
A pre-placement net length estimation technique for mixed-size circuits.
SLIP
Bahareh Fathi, Laleh Behjat, Logan M. Rakai
2007 C conf
Two Clustering Preprocessing Techniques for Large-Scale Circuits.
ISCAS
Laleh Behjat, Jianhua Li, Logan M. Rakai, Jie Huang
2006 — conf
A Structural Study and Hyperedge Clustering Technique for Large Scale Circuits.
SiPS
Logan M. Rakai, Jianhua Li, Laleh Behjat, Jie Huang