Lloyd W. Massengill

14 papers Journal 6Unranked 8
YearRankTypeTitle / Venue / Authors
2021 — conf
Frequency, LET, and Supply Voltage Dependence of Logic Soft Errors at the 7-nm Node.
IRPS
Yoni Xiong, Alexandra Feeley, Lloyd W. Massengill, Bharat L. Bhuva, Shi-Jie Wen, Rita Fung
2020 — conf
Temperature Dependence of Single-Event Transient Pulse Widths for 7-nm Bulk FinFET Technology.
IRPS
Jingchen Cao, Lyuan Xu, Shi-Jie Wen, Rita Fung, Balaji Narasimham, Lloyd W. Massengill, Bharat L. Bhuva
2019 — conf
Alpha Particle Soft-Error Rates for D-FF Designs in 16-Nm and 7-Nm Bulk FinFET Technologies.
IRPS
Jingchen Cao, Lyuan Xu, Bharat L. Bhuva, Shi-Jie Wen, Richard Wong, Balaji Narasimham, Lloyd W. Massengill
2019 — conf
Single-Event Upset Responses of Dual- and Triple-Well D Flip-Flop Designs in 7-nm Bulk FinFET Technology.
IRPS
Lyuan Xu, Jingchen Cao, Bharat L. Bhuva, Indranil Chatterjee, Shi-Jie Wen, Richard Wong, Lloyd W. Massengill
2018 — conf
Designing soft-error-aware circuits with power and speed optimization.
IRPS
H. Jiang, H. Zhang, Balaji Narasimham, Lloyd W. Massengill, Bharat L. Bhuva
2018 — conf
Evaluation on flip-flop physical unclonable functions in a 14/16-nm bulk FinFET technology.
IRPS
H. Zhang, H. Jiang, M. R. Eaker, Kurt J. Lezon, Balaji Narasimham, Nihaar N. Mahatme, Lloyd W. Massengill, Bharat L. Bhuva
2018 — conf
Impact of supply voltage and particle LET on the soft error rate of logic circuits.
IRPS
Hui Jiang, H. Zhang, R. C. Harrington, J. A. Maharrey, J. S. Kauppila, Lloyd W. Massengill, Bharat L. Bhuva
2015 — conf
Multi-cell soft errors at the 16-nm FinFET technology node.
IRPS
N. Tam, Bharat L. Bhuva, Lloyd W. Massengill, Dennis R. Ball, Michael W. McCurdy, Michael L. Alles, Indranil Chatterjee
2011 J jnl
The sensitivity of radiation-induced leakage to STI topology and sidewall doping.
Microelectron. Reliab.
Nadia Rezzak, Michael L. Alles, Ronald D. Schrimpf, Sarah Kalemeris, Lloyd W. Massengill, John Sochacki, Hugh J. Barnaby
2008 J jnl
Design Technique for Mitigation of Soft Errors in Differential Switched-Capacitor Circuits.
IEEE Trans. Circuits Syst. II Express Briefs
Patrick R. Fleming, Brian D. Olson, W. Timothy Holman, Bharat L. Bhuva, Lloyd W. Massengill
1992 J jnl
An analog neural hardware implementation using charge-injection multipliers and neutron-specific gain control.
IEEE Trans. Neural Networks
Lloyd W. Massengill, David Bryan Mundie
1991 J jnl
A dynamic CMOS multiplier for analog VLSI based on exponential pulse-decay modulation.
IEEE J. Solid State Circuits
Lloyd W. Massengill
1991 J jnl
Weight decay and resolution effects in feedforward artificial neural networks.
IEEE Trans. Neural Networks
David Bryan Mundie, Lloyd W. Massengill
1989 J jnl
RSIM: A circuit simulation program for VLSI interconnect networks.
Simul.
Lloyd W. Massengill, Neal Bengtson