Liyi Xiao

82 papers A* 1B 2C 5Journal 50Unranked 24
YearRankTypeTitle / Venue / Authors
2025 J jnl
Error Correction Codes for Double Burst Errors Correction in Memories.
IEEE Access
He Liu, Liyi Xiao, Tianqi Wang, Jiaqiang Li, Jie Li
2024 J jnl
SET-detection low complexity burst error correction codes for SRAM protection.
Integr.
He Liu, Jiaqiang Li, Liyi Xiao, Tianqi Wang, Jie Li
2024 J jnl
SigDLA: A Deep Learning Accelerator Extension for Signal Processing.
CoRR
Fangfa Fu, Wenyu Zhang, Zesong Jiang, Zhiyu Zhu, Guoyu Li, Bing Yang, Cheng Liu, Liyi Xiao, Jinxiang Wang, Huawei Li, Xiaowei Li
2023 J jnl
A Compact RF Energy Harvesting Wireless Sensor Node with an Energy Intensity Adaptive Management Algorithm.
Sensors
Xiaoqiang Liu, Mingxue Li, Xinkai Chen, Yiheng Zhao, Liyi Xiao, Yufeng Zhang
2022 J jnl
A Low-Cost Error-Tolerant Flip-Flop Against SET and SEU for Dependable Designs.
IEEE Trans. Circuits Syst. I Regul. Pap.
Jie Li, Liyi Xiao, Linzhe Li, Hongchen Li, He Liu, Chenxu Wang
2022 J jnl
A Write-Buffer Scheme to Protect Cache Memories Against Multiple-Bit Errors.
IEEE Access
Jie Li, Liyi Xiao, Linzhe Li, Hongchen Li, He Liu, Chenxu Wang
2022 J jnl
Synergistic Effect of BTI and Process Variations on the Soft Error Rate Estimation in Digital Circuits.
IEEE Access
Linzhe Li, Liyi Xiao, He Liu, Zhigang Mao
2021 J jnl
Design of High-Reliability Memory Cell to Mitigate Single Event Multiple Node Upsets.
IEEE Trans. Circuits Syst. I Regul. Pap.
Hongchen Li, Liyi Xiao, Chunhua Qi, Jie Li
2021 J jnl
Design of a high-performance 12T SRAM cell for single event upset tolerance.
Sci. China Inf. Sci.
Chunhua Qi, Yanqing Zhang, Guoliang Ma, Chaoming Liu, Tianqi Wang, Liyi Xiao, Mingxue Huo, Guofu Zhai
2021 J jnl
Designs for efficient low power cardinality and similarity sketches by Two-Step Hashing (TSH).
Integr.
Jie Li, Pedro Reviriego, Shanshan Liu, Liyi Xiao, Fabrizio Lombardi
2021 J jnl
Protecting Memories against Soft Errors: The Case for Customizable Error Correction Codes.
IEEE Trans. Emerg. Top. Comput.
Jiaqiang Li, Pedro Reviriego, Liyi Xiao, Haotian Wu
2020 J jnl
An Adjustable and Fast Error Repair Scrubbing Method Based on Xilinx Essential Bits Technology for SRAM-Based FPGA.
IEEE Trans. Reliab.
Rongsheng Zhang, Liyi Xiao, Jie Li, Xuebing Cao, Linzhe Li
2020 J jnl
Learning reinforced attentional representation for end-to-end visual tracking.
Inf. Sci.
Peng Gao, Qiquan Zhang, Fei Wang, Liyi Xiao, Hamido Fujita, Yan Zhang
2020 — conf
Reduction of Parity Overhead in a Subset of Orthogonal Latin Square Codes.
DCIS
Pedro Reviriego, Shanshan Liu, Alfonso Sánchez-Macián, Liyi Xiao, Juan Antonio Maestro
2020 J jnl
Scheme for periodical concurrent fault detection in parallel CRC circuits.
IET Comput. Digit. Tech.
Jie Li, Shanshan Liu, Pedro Reviriego, Liyi Xiao, Fabrizio Lombardi
2020 J jnl
Siamese attentional keypoint network for high performance visual tracking.
Knowl. Based Syst.
Peng Gao, Ruyue Yuan, Fei Wang, Liyi Xiao, Hamido Fujita, Yan Zhang
2019 J jnl
A Layout-Based Soft Error Vulnerability Estimation Approach for Combinational Circuits Considering Single Event Multiple Transients (SEMTs).
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Xuebing Cao, Liyi Xiao, Jie Li, Rongsheng Zhang, Shanshan Liu, Jinxiang Wang
2019 — conf
A Radiation Hardened Clock Inverter Cell with High Reliability for Mitigating SET in Clock Network.
ASICON
Jie Li, Liyi Xiao, Hongchen Li, Lulu Liao, Chenxu Wang
2019 C conf
Efficient Concurrent Error Detection for SEC-DAEC Encoders.
IOLTS
Jiaqiang Li, Pedro Reviriego, Costas Argyrides, Liyi Xiao
2019 B conf
Learning Cascaded Siamese Networks for High Performance Visual Tracking.
ICIP
Peng Gao, Yipeng Ma, Ruyue Yuan, Liyi Xiao, Fei Wang
2019 J jnl
Learning Cascaded Siamese Networks for High Performance Visual Tracking.
CoRR
Peng Gao, Yipeng Ma, Ruyue Yuan, Liyi Xiao, Fei Wang
2019 J jnl
Learning Reinforced Attentional Representation for End-to-End Visual Tracking.
CoRR
Peng Gao, Qiquan Zhang, Liyi Xiao, Yan Zhang, Fei Wang
2019 J jnl
Low Delay 3-Bit Burst Error Correction Codes.
J. Electron. Test.
Jiaqiang Li, Pedro Reviriego, Liyi Xiao
2019 — conf
Low Redundancy Double Error Correction Spotty Codes Combined with Gray Coding for 64 Data Bits Memories of 4-bit Multilevel Cells.
DFT
Shanshan Liu, Pedro Reviriego, Kazuteru Namba, Salvatore Pontarelli, Liyi Xiao, Fabrizio Lombardi
2019 — conf
Novel High-Performance and Cost Effective Soft Error Hardened Flip-Flop Design for Nanoscale CMOS Technology.
ASICON
Hongchen Li, Liyi Xiao, Jie Li, He Liu
2019 — conf
Protecting Large Word Size Memories against MCUs with 3-bit Burst Error Correction.
DFT
Jiaqiang Li, Pedro Reviriego, Liyi Xiao, Alexander Klockmann
2019 J jnl
Siamese Attentional Keypoint Network for High Performance Visual Tracking.
CoRR
Peng Gao, Yipeng Ma, Ruyue Yuan, Liyi Xiao, Fei Wang
2019 — conf
Simulation of Proton Induced Single Event Upsets in Bulk Nano-CMOS SRAMs.
ICICDT
Xuebing Cao, Liyi Xiao, Linzhe Li, Jie Li, Tianqi Wang
2019 J jnl
Single-event upset prediction in static random access memory cell account for parameter variations.
Sci. China Inf. Sci.
Mingxue Huo, Guoliang Ma, Bin Zhou, Liyi Xiao, Chunhua Qi, Yanqing Zhang, Jianning Ma, Yinghun Piao, Tianqi Wang
2019 — conf
Synergistic Effect of BTI and Process Variations on Impact and Monitoring of Combination Circuit.
ASICON
Linzhe Li, Liyi Xiao, Jie Li, He Liu, Zhigang Mao
2018 J jnl
A Complementary Tracking Model with Multiple Features.
CoRR
Peng Gao, Yipeng Ma, Ke Song, Chao Li, Fei Wang, Liyi Xiao
2018 J jnl
A fast fault injection platform of multiple SEUs for SRAM-based FPGAs.
Microelectron. Reliab.
Rongsheng Zhang, Liyi Xiao, Jie Li, Xuebing Cao, Chunhua Qi, Jiaqiang Li, Mingjiang Wang
2018 J jnl
Adaptive Object Tracking with Complementary Models.
IEICE Trans. Inf. Syst.
Peng Gao, Yipeng Ma, Chao Li, Ke Song, Yan Zhang, Fei Wang, Liyi Xiao
2018 J jnl
Design of Area-Efficient and Highly Reliable RHBD 10T Memory Cell for Aerospace Applications.
IEEE Trans. Very Large Scale Integr. Syst.
Jing Guo, Lei Zhu, Yu Sun, Huiliang Cao, Hai Huang, Tianqi Wang, Chunhua Qi, Rongsheng Zhang, Xuebing Cao, Liyi Xiao, Zhigang Mao
2018 J jnl
Efficient Implementations of 4-Bit Burst Error Correction for Memories.
IEEE Trans. Circuits Syst. II Express Briefs
Jiaqiang Li, Liyi Xiao, Pedro Reviriego, Rongsheng Zhang
2018 J jnl
Extending 3-bit Burst Error-Correction Codes With Quadruple Adjacent Error Correction.
IEEE Trans. Very Large Scale Integr. Syst.
Jiaqiang Li, Pedro Reviriego, Liyi Xiao, Costas Argyrides, Jie Li
2018 J jnl
Fault tolerant encoders for Single Error Correction and Double Adjacent Error Correction codes.
Microelectron. Reliab.
Shanshan Liu, Pedro Reviriego, Juan Antonio Maestro, Liyi Xiao
2018 J jnl
High Performance Visual Tracking with Circular and Structural Operators.
CoRR
Peng Gao, Yipeng Ma, Ke Song, Chao Li, Fei Wang, Liyi Xiao, Yan Zhang
2018 J jnl
High performance visual tracking with circular and structural operators.
Knowl. Based Syst.
Peng Gao, Yipeng Ma, Ke Song, Chao Li, Fei Wang, Liyi Xiao, Yan Zhang
2018 B conf
Large Margin Structured Convolution Operator for Thermal Infrared Object Tracking.
ICPR
Peng Gao, Yipeng Ma, Ke Song, Chao Li, Fei Wang, Liyi Xiao
2018 J jnl
Large Margin Structured Convolution Operator for Thermal Infrared Object Tracking.
CoRR
Peng Gao, Yipeng Ma, Ke Song, Chao Li, Fei Wang, Liyi Xiao
2018 C conf
Soft error optimization of combinational circuit based on gate sizing and multi-objective particle swarm optimization algorithm.
IOLTS
Xuebing Cao, Liyi Xiao, Linzhe Li, Jie Li, Jiaqiang Li, Jinxiang Wang
2017 — conf
A 13T radiation-hardened memory cell for low-voltage operation and ultra-low power space applications.
ISQED
Chunhua Qi, Liyi Xiao, Mingxue Huo, Tianqi Wang, Rongsheng Zhang, Xuebing Cao
2017 J jnl
A Scheme to Reduce the Number of Parity Check Bits in Orthogonal Latin Square Codes.
IEEE Trans. Reliab.
Pedro Reviriego, Shanshan Liu, Alfonso Sánchez-Macián, Liyi Xiao, Juan Antonio Maestro
2017 — conf
A fast and accurate fault injection platform for SRAM-based FPGAs.
ASICON
Rongsheng Zhang, Liyi Xiao, Jie Li
2017 — conf
A method to estimate cross-section of circuits at RTL levels.
ASICON
Liyi Xiao, Anlong Li, Xuebing Cao, Hongchen Li, Rongsheng Zhang, Jie Li, Tianqi Wang
2017 J jnl
A method to recover critical bits under a double error in SEC-DED protected memories.
Microelectron. Reliab.
Shanshan Liu, Pedro Reviriego, Liyi Xiao, Juan Antonio Maestro
2017 J jnl
Comments on "Extend orthogonal Latin square codes for 32-bit data protection in memory applications" Microelectron. Reliab. 63 278-283 (2016).
Microelectron. Reliab.
Shanshan Liu, Pedro Reviriego, Alfonso Sánchez-Macián, Juan Antonio Maestro, Liyi Xiao
2017 — conf
Low redundancy matrix-based codes for adjacent error correction with parity sharing.
ISQED
Shanshan Liu, Liyi Xiao, Jie Li, Yihan Zhou, Zhigang Mao
2017 — conf
Low-cost resilient radiation hardened flip-flop design.
ASICON
Liyi Xiao, Chunhua Qi, Tianqi Wang, Hongchen Li, Jiaqiang Li
2017 J jnl
Novel Radiation-Hardened-by-Design (RHBD) 12T Memory Cell for Aerospace Applications in Nanoscale CMOS Technology.
IEEE Trans. Very Large Scale Integr. Syst.
Jing Guo, Lei Zhu, Wenyi Liu, Hai Huang, Shanshan Liu, Tianqi Wang, Liyi Xiao, Zhigang Mao
2017 — conf
Reliability analysis of memories suffering MBUs for the effect of negative bias temperature instability.
ASP-DAC
Shanshan Liu, Liyi Xiao, Xuebing Cao, Zhigang Mao
2016 J jnl
An Efficient Single and Double-Adjacent Error Correcting Parallel Decoder for the (24, 12) Extended Golay Code.
IEEE Trans. Very Large Scale Integr. Syst.
Pedro Reviriego, Shanshan Liu, Liyi Xiao, Juan Antonio Maestro
2016 J jnl
Extend orthogonal Latin square codes for 32-bit data protection in memory applications.
Microelectron. Reliab.
Shanshan Liu, Liyi Xiao, Zhigang Mao
2015 — conf
Fault Secure Encoder and Decoder Designs for Matrix Codes.
CAD/Graphics
Shanshan Liu, Liyi Xiao, Jing Guo, Zhigang Mao
2015 — conf
Hardened design based on advanced orthogonal Latin code against two adjacent multiple bit upsets (MBUs) in memories.
ISQED
Liyi Xiao, Jiaqiang Li, Jie Li, Jing Guo
2015 J jnl
Low cost and highly reliable radiation hardened latch design in 65 nm CMOS technology.
Microelectron. Reliab.
Chunhua Qi, Liyi Xiao, Jing Guo, Tianqi Wang
2015 — conf
Novel technique for P-hit single-event transient mitigation using enhance dummy transistor.
ISQED
Tianqi Wang, Liyi Xiao, Mingxue Huo, Chunhua Qi, Shanshan Liu
2015 J jnl
Soft Error Hardened Memory Design for Nanoscale Complementary Metal Oxide Semiconductor Technology.
IEEE Trans. Reliab.
Jing Guo, Liyi Xiao, Tianqi Wang, Shanshan Liu, Xu Wang, Zhigang Mao
2014 J jnl
CORDIC based fast algorithm for power-of-two point DCT and its efficient VLSI implementation.
Microelectron. J.
Hai Huang, Liyi Xiao
2014 J jnl
CORDIC-Based Unified Architectures for Computation of DCT/IDCT/DST/IDST.
Circuits Syst. Signal Process.
Hai Huang, Liyi Xiao, Jiaming Liu
2014 J jnl
Enhanced Memory Reliability Against Multiple Cell Upsets Using Decimal Matrix Code.
IEEE Trans. Very Large Scale Integr. Syst.
Jing Guo, Liyi Xiao, Zhigang Mao, Qiang Zhao
2014 J jnl
Novel Low-Power and Highly Reliable Radiation Hardened Memory Cell for 65 nm CMOS Technology.
IEEE Trans. Circuits Syst. I Regul. Pap.
Jing Guo, Liyi Xiao, Zhigang Mao
2013 J jnl
A Low Power Built-in Self-Test Scheme Based on Overlapping Bit Swapping Linear Feedback Shift Register.
J. Low Power Electron.
Bin Zhou, Xin-chun Wu, Yu Sun, Tianqi Wang, Liyi Xiao
2013 J jnl
CORDIC Based Fast Radix-2 DCT Algorithm.
IEEE Signal Process. Lett.
Hai Huang, Liyi Xiao
2013 J jnl
Novel Mixed Codes for Multiple-Cell Upsets Mitigation in Static RAMs.
IEEE Micro
Jing Guo, Liyi Xiao, Zhigang Mao, Qiang Zhao
2012 J jnl
Test Pattern Generation Based on Multi-TRC Scan Architecture for Reducing Test Cost.
J. Low Power Electron.
Bin Zhou, Liyi Xiao, Yizheng Ye, Xin-chun Wu, Bei Cao
2011 J jnl
New Mix codes for multiple bit upsets mitigation in fault-secure memories.
Microelectron. J.
Ming Zhu, Liyi Xiao, Li Li Song, Yan Jing Zhang, Hong Wei Luo
2011 C conf
New SEC-DED-DAEC codes for multiple bit upsets mitigation in memory.
VLSI-SoC
Ming Zhu, Liyi Xiao, Hong Wei Luo
2011 J jnl
Optimization of Test Power and Data Volume in BIST Scheme Based on Scan Slice Overlapping.
J. Electron. Test.
Bin Zhou, Liyi Xiao, Yizheng Ye, Xin-chun Wu
2010 C conf
DSTN sleep transistor sizing with a new approach to estimate the maximum instantaneous current.
ISCAS
Yu Sun, Liyi Xiao, Cong Shi
2010 — conf
Efficient Two-Dimensional Error Codes for Multiple Bit Upsets Mitigation in Memory.
DFT
Ming Zhu, Liyi Xiao, Shuhao Li, Yanjing Zhang
2009 A* conf
Soft error optimization of standard cell circuits based on gate sizing and multi-objective genetic algorithm.
DAC
Weiguang Sheng, Liyi Xiao, Zhigang Mao
2008 — conf
A Low Power Deterministic Test Pattern Generator for BIST Based on Cellular Automata.
DELTA
Bei Cao, Liyi Xiao, Yongsheng Wang
2008 — conf
A novel soft error sensitivity characterization technique based on simulated fault injection and constrained association analysis.
ICECS
Weiguang Sheng, Liyi Xiao, Zhigang Mao
2008 — conf
An Automated Fault Injection Technique Based on VHDL Syntax Analysis and Stratified Sampling.
DELTA
Weiguang Sheng, Liyi Xiao, Zhigang Mao
2008 — conf
Electronic Shelf Label System based on public illuminating network.
APCCAS
Hong Hong, Yi Ren, Ricai Tian, Liyi Xiao
2008 C conf
Versatile and Efficient Techniques for Speeding-Up Circuit Level Simulated Fault-Injection Campaigns.
PRDC
Weiguang Sheng, Liyi Xiao, Zhigang Mao
2003 — conf
A Test Architecture for System-on-a-Chip.
Asian Test Symposium
Yongsheng Wang, Liyi Xiao, Mingyan Yu, Jinxiang Wang, Yizheng Ye
2002 J jnl
A New Synchronization Algorithm for VHDL-AMS Simulation.
J. Comput. Sci. Technol.
Liyi Xiao, Yizheng Ye, Bin Li
2001 — conf
A mixed-signal simulator for VHDL-AMS.
ASP-DAC
Liyi Xiao, Bin Li, Yizheng Ye, Guoyong Huang, Jinjun Guo, Peng Zhang
2001 — conf
CLUGGS and CLUCR-Two Matrix Solution Methods for General Circuit Simulation.
Annual Simulation Symposium
Bin Li, Liyi Xiao, Yizheng Ye, Guoyong Huang