Liyang Pan

25 papers A 2C 3Journal 10Unranked 10
YearRankTypeTitle / Venue / Authors
2024 — conf
A Dual-Gate Vertical Channel IGZO Transistor for BEOL Stackable 3D Parallel Integration for Memory and Computing Applications.
VLSI Technology and Circuits
Ziyi Liu, Yiwei Du, Renrong Liang, Zhigang Zhang, Liyang Pan, Jianshi Tang, Bin Gao, Qi Hu, Jun Xu, He Qian, Huaqiang Wu, Yuegang Zhang
2024 J jnl
ANP-I: A 28-nm 1.5-pJ/SOP Asynchronous Spiking Neural Network Processor Enabling Sub-0.1-μ J/Sample On-Chip Learning for Edge-AI Applications.
IEEE J. Solid State Circuits
Jilin Zhang, Dexuan Huo, Jian Zhang, Chunqi Qian, Qi Liu, Liyang Pan, Zhihua Wang, Ning Qiao, Kea-Tiong Tang, Hong Chen
2023 — conf
ANP-I: A 28nm 1.5pJ/SOP Asynchronous Spiking Neural Network Processor Enabling Sub-O.1 μJ/Sample On-Chip Learning for Edge-AI Applications.
ISSCC
Jilin Zhang, Dexuan Huo, Jian Zhang, Chunqi Qian, Qi Liu, Liyang Pan, Zhihua Wang, Ning Qiao, Kea-Tiong Tang, Hong Chen
2023 — conf
An Energy-Efficient Gain-Cell Embedded DRAM Design with Weight Encoding for CNN Applications.
ICTA
Tao Huang, Run Run, Yi Hu, Li Yin, Liyang Pan, Guolin Li, Xiang Xie
2023 J jnl
An Error-Free 64KB ReRAM-Based nvSRAM Integrated to a Microcontroller Unit Supporting Real-Time Program Storage and Restoration.
IEEE Trans. Circuits Syst. I Regul. Pap.
Hanwen Gong, Hu He, Liyang Pan, Bin Gao, Jianshi Tang, Sining Pan, Jianing Li, Peng Yao, Dabin Wu, He Qian, Huaqiang Wu
2019 A conf
OCStore: Accelerating Distributed Object Storage with Open-Channel SSDs.
ICDCS
Youyou Lu, Jiacheng Zhang, Zhe Yang, Liyang Pan, Jiwu Shu
2016 — conf
Fabrication of ultra-thin silicon chips using thermally decomposable temporary bonding adhesive.
IEEE SENSORS
Xingjun Xue, Shujie Yang, Dong Wu, Liyang Pan, Zheyao Wang
2016 J jnl
LSB page refresh based retention error recovery scheme for MLC NAND Flash.
Sci. China Inf. Sci.
Haozhi Ma, Lifang Liu, Liyang Pan, Jun Xu
2015 J jnl
A 1G-cell floating-gate NOR flash memory in 65 nm technology with 100 ns random access time.
Sci. China Inf. Sci.
Lifang Liu, Dong Wu, Xuemei Liu, Zongliang Huo, Ming Liu, Liyang Pan
2015 — conf
Air-gap/SiO2 liner TSVs with improved electrical performance.
3DIC
Cui Huang, Dong Wu, Liyang Pan, Zheyao Wang
2015 — conf
Data pre-emphasis based retention reliability enhance scheme for MLC NAND Flash memories.
ASICON
Haozhi Ma, Zhongyi Gao, Liyang Pan, Jun Xu
2015 C conf
Software Hardware Co-design for Side-Channel Analysis Platform on Security Chips.
CIS
Qian Lei, Liji Wu, Shaohui Zhang, Xiangmin Zhang, Xiangyu Li, Liyang Pan, Zhimeng Dong
2015 — conf
Synaptic learning behaviors achieved by metal ion migration in a Cu/PEDOT: PSS/Ta memristor.
NVMTS
Wenqiang Luo, Fang-Yuan Yuan, Huaqiang Wu, Liyang Pan, Ning Deng, Fei Zeng, Rongshan Wei, Xuanjing Cai
2014 J jnl
A Fast Application-Based Supply Voltage Optimization Method for Dual Voltage FPGA.
IEEE Trans. Very Large Scale Integr. Syst.
Jianfeng Zhu, Liyang Pan, Yaru Yan, Dong Wu, Hu He
2014 C conf
An ultra-low-power extended counting ADC For large scale sensor arrays.
ISCAS
Cencen Gao, Dong Wu, Hui Liu, Nan Xie, Liyang Pan
2014 J jnl
Assessment methodology of the lateral migration component in data retention of 3D SONOS memories.
Microelectron. Reliab.
Lifang Liu, Antonio Arreghini, Geert Van den Bosch, Liyang Pan, Jan Van Houdt
2014 J jnl
Total ionizing radiation effects of 2-T SONOS for 130 nm/4 Mb NOR flash memory technology.
Sci. China Inf. Sci.
Fengying Qiao, Liyang Pan, Xiao Yu, Haozhi Ma, Dong Wu, Jun Xu
2011 A conf
A chip-level path-delay-distribution based Dual-VDD method for low power FPGA (abstract only).
FPGA
Jianfeng Zhu, Dong Wu, Yaru Yan, Xiao Yu, Hu He, Liyang Pan
2011 J jnl
A cost-efficient self-configurable BIST technique for testing multiplexer-based FPGA interconnect.
J. Electron. Test.
Jianfeng Zhu, Hu He, Dong Wu, Liyang Pan
2011 J jnl
Erratum to: A Cost-Efficient Self-Configurable BIST Technique for Testing Multiplexer-Based FPGA Interconnect.
J. Electron. Test.
Jianfeng Zhu, Hu He, Dong Wu, Liyang Pan
2010 C conf
A novel high-speed and low-power negative voltage level shifter for low voltage applications.
ISCAS
Peijun Liu, Xueqiang Wang, Dong Wu, Zhigang Zhang, Liyang Pan
2009 J jnl
A High-Speed Two-Cell BCH Decoder for Error Correcting in MLC
IEEE Trans. Circuits Syst. II Express Briefs
Xueqiang Wang, Liyang Pan, Dong Wu, Chaohong Hu, Runde Zhou
2009 — conf
Embedded high-speed BCH decoder for new-generation NOR flash memories.
CICC
Xueqiang Wang, Dong Wu, Chaohong Hu, Liyang Pan, Runde Zhou
2008 — conf
Pure logic CMOS based embedded Non-Volatile Random Access Memory for low power RFID application.
CICC
Liyang Pan, Xian Luo, Yaru Yan, Jirong Ma, Dong Wu, Jun Xu
2006 — conf
180nm 4Mb High Speed High Reliability Embedded SONOS Flash Memory.
CICC
Liyang Pan, Dong Wu, Guangjun Yang, Lei Sun, Huiqing Pang, Jun Zhu